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Emerging Flip Chip and WL-CSP Technologies
December 31, 1969 |Estimated reading time: 3 minutes
Flip chip and wafer-level chip scale packaging (WL-CSP) are defined clearly for the benefit of both customers and manufacturers.
By Bob Lanzone
Wafer-level redistribution technology originally was intended as a physical redistribution or transformation of perimeter bonding pads to an area array for flip chip technology facilitation. It now is becoming much more. Although definitions for items like chip scale packaging (CSP) have developed, and subcategories for this packaging technology have been created, the definition of WL-CSP remains somewhat unclear.
Even from the perspective of companies performing wafer redistribution and bumping, the distinction between flip chip and WL-CSP can be subtle. Therefore, it is critical to define the two for the benefit of the customer.
Defining Flip Chip and WL-CSPFlip chip is defined as wafers that may or may not have redistribution, that contain fine-pitch solder bumps and are limited in ball diameter. Generally, this refers to bump pitches of less than 350 μm with solder bumps that are less than 150 μm in size.WL-CSP is defined as wafers that may require redistribution, contain coarse-pitch solder bumps or spheres and have larger ball diameters. Generally, this refers to bump pitches greater than 400 μm with solder bumps greater than 200 μm in size (Figure 1 - right).Figure 1. An array of available CSP services, including electroplated CSP (with ball heights <200 μm, compatible with SMT), ball placement CSP (with ball heights >200 μm, compatible with SMT, designed to avoid underfill, and currently is available in no lead and low alpha) and single mask CSP (the most economical CSP, available in limited design configurations).
Additionally, WL-CSPs are:
- Cost competitive, with the lowest cost alternate package available for the device
- Not moisture-sensitive
- Reworkable in the board assembly operation
- Compatible with all existing SMT process and cleaning processes
- Compatible with existing integrated circuit (IC) die designs and wafer layouts currently produced
- Proven reliable for the application
- Not in need of underfill for most applications.
- Able to protect the die from alpha particle emission coming from the solder
- Able to protect board customers from IC manufacturers' die stepping and shrinks.
There are three styles of WL-CSP: single mask WL-CSP, electroplated WL-CSP and ball placement WL-CSP. The first two styles use the same manufacturing processes to produce flip chip and WL-CSP. Quite literally, it is the solder bump pitch and bump sphere size that distinguish the reference of these products as flip chip vs. WL-CSP.
ElectroplatingOne principal technology employed to create the large solder spheres for WL-CSP is electroplating. There are limitations as to the maximum size of the structure being formed. Electroplating uses a photoimageable stencil to create the plating mask or template. Using overplating methods, mushroom bump structures can be created that after reflow, form bumps as large as 200 μm. Even larger structures can be created with this method, but there is a point at which manufacturability issues related to equipment use and cycle time come into play. In this instance, it is more efficient to place solder spheres to form the bumps through ball placement WL-CSP.
RedistributionRedistribution metallization is available in either aluminum or copper. Because copper interconnect is the preferred technology path for advanced wafer fabrication and IC designs, production for multi-level copper (MLCU) redistribution was developed.* The dielectric material used for MLCU is Dow's Bisbenzocyclobutene (BCB) or tradename "Cylcotene."
Notable properties of BCB include a low dielectric constant, low moisture absorption, low cure temperature, high degree of planarization, low level of ionics, high optical clarity, good thermal stability and excellent chemical resistance.
Using MLCU for redistribution traces with the formation of an under bump metallurgy (UBM) structure is the basis for the most advanced WL-CSP offerings. In the case of ball placement WL-CSP, a solder wettable terminal is created using a UBM structure suitable for traditional ball flux and placement technology. This technology allows for flexibility in ball sizes and solder compositions, including lead-free alloys. Customer's applications and reliability requirements can be addressed more easily with this methodology. Where coarse-pitch requirements allow, ball sizes can be made larger to increase the interconnection standoff, thus improving reliability (Figure 2).Figure 2. Comparison of flip chip ultra-fine, 50 μm (left) and standard, or typical, 250 μm (right) pitch solder bumps.
ConclusionFlip chip and WL-CSP technologies can be very similar in process and manufacture. The key goal is to provide reliable interconnect and packaging technologies that meet customers' requirements. It is essential that the technology and manufacturing capabilities of wafer bumping suppliers create a broad and extendible set of product offerings that meet these needs. Flip chip and WL-CSP are rapidly growing technologies that meet the requirements for smaller, faster and cheaper alternatives for a broad array of applications.
- Unitive Advanced Semiconductor Packaging.
BOB LANZONE, VP marketing, may be contacted at Unitive Advanced Semiconductor Packaging, 4512 S. Miami Blvd., Suite 120, Research Triangle Park, NC 27709-4584; (919) 941-0606; Fax: (919) 941-5097; E-mail: rlanzone@unitive.com