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Designing with CBGAs
December 31, 1969 |Estimated reading time: 9 minutes
Designing with CBGAs
An Experimental Approach for commercial and industrial electronics, PBGAs generally perform reliably over a -40° to 85°C temperature range. For aerospace and military assemblies demanding reliable operation over a wider temperature range, it is necessary to use CBGAs.
Michael Becker
Barry Mathieu
Richard Morgen
Recently, the task of designing a printed circuit board (PCB) assembly that featured two digital signal processors (DSP), each packaged as a ceramic dimpled ball grid array (CDBGA) measuring 27 mm2 and containing 429 I/Os (Figure 1), presented itself. The ceramic package was selected over a plastic version because of the environment the assembly faced and because the customer demanded it.
A literature review revealed that a constrained-core assembly construction was necessary for parts to stay on the board during thermal cycling. The common PCB substrate materials` coefficient of thermal expansion (CTE) is much larger than that of the ceramic packaged device, which, coupled with the BGA`s size, produced large stresses in the solder bumps and joints during temperature excursions. Accordingly, three core materials were considered: copper-molybdenum-copper (CMC), beryllium/beryllium-oxide (Be/BeO) and aluminum/silicon-carbide (Al/SiC). During the initial stages of preparation, a construction method* was suggested to provide a board with a low CTE. It was decided to conduct an experiment to compare all four designs and to investigate the effects of different pad designs and via routing.
The Experiment
The part used was a DSP packaged in a CDBGA, designed to be exposed to full military qualified manufacturers list (QML) processing, and an operational temperature range of -55∞ to 125∞C (case temperature). Ceramic components exhibit a CTE between 4.5 and 6.5 ppm per ∞C. To promote heat dissipation in the design, copper thermal planes were added to the board and a CTE value of 13 to 17 ppm per ∞C was expected for the design.
Considering the expected environmental temperature range, the disparity between the CTE values of the part and board, plus part size, there was concern about solder joint fatigue failure. The constrained-core design approach appeared to be a solution that would provide an increased heat-dissipation path. A number of candidate core materials were available: CMC, AlSiC and Be/BeO, as well as the low-epoxy aramid fiber.*
Although solder joint stress is a function of mounting pad geometry, BGA literature indicates other factors besides pad diameter exist. They include routing style and soldermask on the pad.
Inducing Thermal Stress
A Design of Experiment (DOE) approach examined the effects of the design variables on solder joint fatigue life. To induce thermal stress, an accelerated temperature profile from an electrical continuity tester continuously monitored solder joint integrity. The DOE began with selection of the variables for consideration. With additional data from manufacturing, electrical engineering, mechanical engineering, and program management, an initial experimental matrix with the following variables was selected:
- Routing (pad) style: dog-bone vs. via- in-pad
- Pad diameter: less than vs. greater than that suggested by the manufacturer
- PCB construction: core vs. non-core
- Core material: Al/SiC, Be/BeO and CMC.
For the experiment, a daisy-chained package was selected. Although not a full-array BGA, its outer dimensions were nearly identical to that of a package in which solder thermal-fatigue stress levels would be greatest. To provide adequate detail of the solder joint failure location, the part was partitioned into three sections: inner, middle and outer (Figure 2).
With respect to thermal stress, the inner section, consisting of a single chain with 72 joints, was considered the most robust. Both the middle and outer sections were split into three separate chains, each containing approximately 64 joints. For the core construction, glass-polyimide PCBs were bonded to each side of the core material, creating a module. The via-in-pad construction was then filled and cap-plated. Finally, a balanced design was used throughout, i.e., the copper distribution (signal/power/ground/thermal) is symmetrical about the Z-axis of each PCB.
Simulating the Production Version
Next, nonfunctional traces were placed on the signal layers. Copper content on the voltage supply and ground layers was present at a level similar to that of the production version. The signal layers nearest the core were electrically insulated with B-stage polyimide glass. Adequate heat dissipation was achieved by using an 8 oz copper content. Because these thermal planes must be nearly continuous, two continuous 3 oz planes were added. The two 0.5 oz power and two 0.5 oz ground traces were considered adequate for the remaining 2 oz needed for thermal dissipation. All PCBs were then finished with fused, electro-deposited tin/lead.
On each module, four sites for the daisy-chained parts were used (Figure 3). Two sites featured dog-bone geometry and two used via-in-pad; pad diameters were altered between the high and low value (Figure 4). Thus, a single module was capable of providing significant information on solder joint life as a function of the interconnecting feature geometry. Additional modules were necessary to show the relationship of solder joint life to construction material and to provide experimental replication.
As the PCBs for experimental use were received, pad geometry was measured and hydroscanning (for core-bonding uniformity) was performed before CTE measurements were taken.
During pad-geometry measurements, pad diameters fell in three discrete values rather than the two originally planned. The experiment was reconfigured to further consider the increased number of pad diameters by decreasing the number of planned experimental replications. Table 1 presents the realized PCB pad and routing geometric values: The largest of the three provides the closest to a 1:1 ratio with the pad diameter of the part.
CTE measurements revealed that the acrylic adhesive used for core bonding was not providing sufficient restraint to board thermal expansion. In discussions with the vendor, it was decided that an epoxy adhesive was more suitable for core bonding. The core-bonding adhesive was added as a factor in the experimental matrix, minimizing the loss of information from the experimental process. Modifications of the experiment were constant to conform to realities confronted at any given time. As each small "disaster" struck, the experiment simply adapted to the variables.
Because the substrate did not use a core, there was no change in adhesive for this board style. Additionally, the CMC core was not available with the proper finish to use the epoxy adhesive. The final experiment was conducted with the following test vehicles: the CMC module, the Al/SiC modules, the Be/BeO modules and the low-epoxy aramid fiber PCBs.
For assembly, solder paste composition, volume and reflow profile were held constant, as appropriate. Electrical continuity of each bump chain was continuously monitored during the temperature cycling using an event detector with temperature recording module. This permitted a correlation of a resistance change event with temperature. (An event is any excursion in the daisy-chain resistance exceeding 300 W for longer than 200 nanoseconds.) Temperature cycling of the six test vehicles, consisting of a minimum of 15 minute dwells at extremes of -55∞ and 125∞C with connecting ramp rates of 10∞ to 13∞C per minute, was then conducted over a four-month period.
The Data
The experiment results include CTE measurements of each test board before assembly (Table 2). That the CTE measurements of the first experimental assemblies were so high confirmed a serious flaw. It was discovered that the glass transition (Tg) of the acrylic adhesive used to attach the PCBs to the cores was very low, which affected the CTE such that the PCBs "floated" above the core. Although they did not break free, the combined CTE of the assembly on the surface grew dramatically. These data (combined with early failures in the temperature chamber) forced the application of a second lot of assemblies using an epoxy adhesive with a Tg greater than 100∞C.
The test equipment continuously monitored each solder bump chain separately through the temperature cycling. The output from this test equipment includes the temperature cycle at which each failure occurred. From this information, the first cycle at which a momentary high resistance (a poll) is measured and recorded (i.e., the cycle at which a hard, continuous failure is determined) is then charted on a Weibull plot (Figure 5). It illustrates the point at which half of the solder joint chains are experiencing either a momentary high resistance or continuous open.
Weibull plots were created to compare the levels set for each factor. Data were grouped by every level set and common factors were graphed on individual plots. The factors included CMC acrylic, Be/BeO acrylic, Al/SiC acrylic, DOE PCB, Be/BeO epoxy, Al/SiC epoxy, dog-bone, via-in-pad, large pads, medium pads and small pads. The graphs provide a method to analyze each population group against its counterpart but do not account for the considerable interactions.
After the temperature cycling was completed, the test assemblies were cross-sectioned using diamond-wheel saws and fine-buffing wheels to reveal the solder joint grain structures. The cross-sectioning showed that failure occurred at the junction to the ceramic device (Figure 6). There was no evidence of failure at the junction to the board.
Conclusion
There was a dramatic difference in joint-fatigue life between the modules assembled with acrylic and epoxy. There also was a significant difference among the modules using the three different core materials. The core modules assembled using epoxy lasted 10X longer than those assembled with acrylic. The Al/SiC core board exhibited a better lifetime than the other three construction styles.
While routing style and pad dimensions did not affect results as dramatically as core material and adhesives, the latter did have some effect. The 0.021" pad exhibited the longest life, followed by that of the 0.014" pad; the 0.023" pad was clearly the shortest-lived design. Evidence showed that between via-in-pad and dog-bone, the former had a higher lifetime. (Note that a filled and cap-plate via-in-pad construction was used.) It was concluded that the via-in-pad style with the fused electro-deposited tin/lead finish was a significant factor.
Finally, the experiments clearly indicate that it is possible to design assemblies using a large CDBGA, provided appropriate measures are taken to properly restrain the PCB expansion rate. Via-in-pad is a better approach than dog-bone, and the design is robust with respect to pad size within a reasonable range.
* Thermount.
ACKNOWLEDGEMENTS
The authors acknowledge the advice and criticism of Rick Linnehan, and thank Chuck Lecesse and Todd Gattuso for their analysis and advice.
WORKS CONSULTED
1 T. Scheler, P. Viswanadham, M. Garza, S. Dunford and B. Thomas, "Ceramic Ball Grid Array Assembly Reliability in Military Applications," IPC/SMTA Electronics Assembly Expo, October 1998.
2 Ball Grid Array Packaging Guidelines, Jet Propulsion Laboratory, Interconnection Technology Research Institute, 1998.
MICHAEL BECKER, BARRY MATHIEU and RICHARD MORGEN may be contacted at (410) 552-2619; Fax: (410) 552-2020; E-mail: mikenhil@bcpl.net.
Figure 1. The mechanical outline of the DSP design containing 429 I/Os. Although available in a plastic construction, the environment faced by the assembly demanded the ceramic version.
Figure 2. The dummy test BGA is daisy-chained into three sections - inner (a), middle (b) and outer (c) - to provide solder joint failure location details.
Figure 5. A Weibull chart showing temperature cycles vs. the percentage of solder joint chains with a single poll (momentary high resistance).
Figure 6. Cross-section (100X) of a solder joint shown with the component on top and the PCB below. Note that its well-defined grain structure has voids and is not connected to the component in the dimple area.