**Estimated reading time: 7 minutes**

# IBIS Output Impedance Made Easy

I subscribe to the **SI-List** forum on signal integrity. People often pose the question, “How do you find the driver impedance information from the IBIS file?” Most of the time we want this information so that we can explore mitigation techniques to control reflections caused by impedance discontinuities of the transmission path.

IBIS stands for Input/Output Buffer Information Specification and is controlled by the **IBIS Open Forum** organization. It is a device modeling technique used in simulation to provide a simple table-based, non-proprietary buffer model derived from a real semiconductor device. IBIS models can be used to characterize I/V output curves, rising/falling waveforms and pin parasitics of the device packaging.

When a driver’s output impedance is not matched to the transmission line characteristic impedance (Zo), there are reflections which causes ringing at the receiver as shown by the red waveform in Figure 1. Terminating the transmission line at the receiver using a pull-up or pull-down resistor to match Zo is one way to cure this. Although this approach works fine, it is not the preferred method because the resistor value would be in the 45-70 Ohm range to match the typical single-ended transmission line impedances found in modern PCB designs. Such a low resistance causes additional loading on the driver, resulting in higher power dissipation.

Figure 1. Impedance mismatch causing ringing due to reflections (red) vs. properly terminated (blue).

In some cases, a better method is to add a series resistor at the end of the driver to make up the difference in impedance. For example, if the buffer’s output impedance is 20 Ohms driving a 50 Ohm transmission line, you would add a 30 Ohm resistor in series with the output.

Because the buffer is a semiconductor, its output impedance could vary based on rising/falling edge transitions, manufacturing process (slow, typical, fast), and the load it is driving. Since IBIS models are ASCII-based, you can simply use your favorite text editor to view and quickly estimate the output impedance when driving 50 Ohms using two of the four V-T waveform tables.

Here’s how:

The output impedance is often different for the rising edge compared to the falling edge. To determine the output impedance of a low-to-high transition you would use the pull-down [Rising Waveform] table. A sample of what this table looks like is shown below:

** **

The first three lines of the table tells us that the rising waveform has a 50 Ohm resistor connected to the buffer output and pulled-down to 0V as shown in Figure 2.

Figure 2. Pull-down test fixture equivalent circuit.

The combination of the output impedance (Zs) and the 50 Ohm load forms a simple voltage divider network described by Equation 1.

Equation 1

Where:

*VO*= Voltage at the output pin of the buffer*VDC* = Supply voltage*Zs* = Buffer impedance

Solving for *Zs*, we end up with Equation 2.

Equation 2

If *VDC* is 3.3V, and *VO *is **2.568V**, using the typical voltage at 10 nS from the V-T table above, the output impedance for the rising edge into 50 Ohms is equal to **14.25 Ohms**.

To determine the output impedance of a high-to-low transition you would use the pull-up [Falling Waveform] table similar to the following example:

The table tells us the falling waveform has a 50 Ohm resistor connected to the buffer output and pulled-up to V_fixture as shown by the equivalent circuit shown in Figure 3.

Figure 3. Pull-up test fixture equivalent circuit.

This time, the output impedance is calculated using Equation 3.

Equation 3

Where:

*VO *= Output voltage when the driver is sinking current*V_Fix *= Voltage of the test fixture

Using typical values for ** V_Fix = 3.3V** and

**at 10nS,**

*VO*= 0.5598V**.**

*Zs*= 10.21 OhmsAs you can see for this particular IBIS model, the output impedance varies depending on the edge transition. For a rising edge, the output impedance is 14.25 ohms and 10.21 Ohms for a falling edge when using the typical values. The impedances will also vary under min/max conditions.

If your load is something other than 50 Ohms, you should NOT rely on this simple method for signoff. Instead you should simulate it if the design is critical. Sometimes we just need a quick ballpark number to gain some insight of a particular design or to give us some intuition of what to expect from simulation.

You can validate this methodology using any Spice-like simulator which supports IBIS models. There are many to choose from: Agilent ADS, HSPICE, Mentor Hyperlynx, Cadence Spectraquest, and Ansoft Designer from ANSYS to name a few. Chances are, if you work for a large company, you already have access to some of these tools. If you are a student or someone just starting to learn about signal integrity, there is an alternative available. Fortunately, **Spectrum Software** offers Micro-cap 10, a free trial of its SPICE software. Although it is limited to the number of components, nodes and performance, it is more than adequate for this and other signal integrity studies. Personally, I found it quite easy to pick up and get productive fairly quickly.

For the purpose of the analysis, the output buffer and its impedance (Zs) can be simplified by the schematic as shown in Figure 4.

Figure 4. Simplified schematic of output buffer and input receiver.

When the unterminated buffer drives a 50 Ohm transmission line, you typically see the waveforms at the driver’s output (blue) and receiver’s input (red) as shown in Figure 5.

Figure 5. Waveforms at driver output (blue) and receiver input (red).

The initial step in the rising and falling edges of the blue waveform (Vs) is due to the voltage divider action between Zs and Zo. Let us call each step a “porch” and designate the voltages as Vp_rise/Vp_fall for the rising and falling porches respectively. Vp_rise is equivalent to the maximum voltage of the [Rising Waveform] table found in the IBIS model. Likewise, Vp_fall is equivalent to the minimum voltage of the [Falling Waveform] table.

We can demonstrate this by building and simulating the respective topologies as summarized in Figure 6. A common circuit topology was built using the schematic editor. The respective greyed-out devices are disabled during simulation making it a convenient way of switching them in and out for the different topologies. R1 is reserved for the series termination resistor and is set to 0 Ohms initially. Once the output impedance is determined, R1 is set to the difference between Zo and the output impedance Zs.

The top topology simulates the pull-up test fixture and used to verify the Falling Waveform table in the IBIS model. Similarly, the center topology simulates the pull-down test fixture for the Rising Waveform table. The bottom topology has the output buffer driving a real world 50 Ohm transmission line.

The results of the simulations are shown adjacent to their respective topologies. Referring to the last case, Vp_rise=**2.555V **and Vp_fall=3.3V-2.726V=**0.574V** . As you can see there is excellent correlation when you compare them against the IBIS model’s voltages of **2.568V **and **0.5598V **respectively. Using the simulated voltages and solving for Zs, we get **14.58 Ohms** and **10.53 Ohms** respectively.

Figure 6. Summary of results when an unterminated output buffer is driving a pull-up test fixture (top), pull-down test fixture (middle), and an ideal 50 Ohm transmission line (bottom).

Because Zs is different for the rise time and fall time, you can never perfectly compensate for the impedance mismatch. The best approach is sometimes to take the average value between the two. In this case Zs_avg = **12.56 Ohms**.

Once Zs is known, the series resistor can be calculated as follows:

When 38 Ohms is substituted in the transmission line topology, the waveform is clean with minimum reflections as shown in Figure 7.

Figure 7. Results of an output buffer properly terminated driving an ideal 50 Ohm transmission line. Blue is Vin node, Red is Vout node.

In conclusion, the methodology presented here is a simple and effective way to predict the driver’s output impedance from an IBIS model. Try it next time someone asks you the question, “How do you find the driver impedance information from the IBIS file?”

*Bert Simonovich was born in Hamilton, ON, Canada. He received his Electronic Engineering Technology diploma from Mohawk College of Applied Arts and Technology, Hamilton, ON, Canada in 1976. Over a 32-year career, working as an Electronic Engineering Technologist at Bell Northern Research and later Nortel, in Ottawa, Canada, he helped pioneer several advanced technology solutions into products. He has held a variety of engineering, research and development positions, eventually specializing in signal integrity and backplane architecture for the last 10 years. He is the founder of **Lamsim Enterprises Inc.**, where he continues to provide innovative signal integrity and backplane solutions to clients as a consultant. With three patent applications and two patent grants to his name, he has also (co)authored several publications, including an award winning DesignCon2009 paper related to PCB via modeling. His current research interests include signal integrity, high-speed characterization, and modeling of high-speed serial links associated with backplane interconnects. To contact Bert,**click here**.*

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