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Obsessing over Conductor Surface Roughness: What’s the Effect on Dk?

You know you have an obsession when you are flying six miles over Colorado and you look out the window at the beautiful scenery, and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well, call me obsessed, because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, California.

For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year at DesignCon, I presented a paper titled "A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness."

Everyone involved in the design and manufacture of PCBs knows that one of the most important properties of the dielectric material is the relative permittivity (ε_r), commonly referred to as dielectric constant (D_k). But in reality, D_k is not constant at all. It varies over frequency as you will see later.

We often assume the value reported in manufacturers’ data sheets is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (D_keff) generated by a specific test method. When you compare simulation against measurements, you will often see a discrepancy in Dkeff and IL, due to the increased phase delay caused by surface roughness. This has always bothered me. For a long time, I was always looking for ways to come up with Dkeff from data sheet numbers alone. Thus the obsession and motivation for my recent research work.

Since phase delay, also known as time delay (TD), is proportional to Dkeff of the material, my theory was that the surface roughness profile decreases the effective separation between parallel plates, thereby increasing the electric field (e-field) strength, resulting in additional capacitance, which accounts for an increase in effective D_k and TD.

To read this column, which appeared in the March 2017 issue of The PCB Design Magazine, click here.