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Bert's Practical Design Notes: The "Stubinator" vs. Back-Drilling

It’s a well-known fact that thick backplanes with long via stubs will cause unwanted resonances in the channel insertion loss compared to vias with little or no stub length; as shown by the red and green traces in the plot of Figure 1. If these resonances occur at or near the Nyquist frequency of the bit rate, there will be little or no eye-opening left at the receiver.

Figure 1. Topology circuit model of two differential vias with 30 inches of PCB etch. Insertion loss plot of long via-no stub (green); short via-long stub (red); and stub terminated (blue).  Received eye diagrams after optimized FFE receive equalization at 10 GB/s. Modeled and simulated using Agilent ADS.

In a typical backplane application, the signal entering the via structure from the top will travel along the “through” portion until it reaches the junction of the internal track and stub. At that point, the signal splits, with some of the signal continuing along the trace, and the rest continuing along the stub. If the signal were Arnold Schwarzenegger, he would say, “I’ll be back!” Having done this gig before, he knows that when he reaches the end of the stub, it’s like hitting a brick wall. There’s nowhere for him to go but back.

Like Arnold, when the signal reaches the end of the stub, it reflects back up the stub. When it arrives at the same junction, a portion combines with the original signal and the rest continues back toward the source. If the round-trip delay through the stub is half a cycle, the two waves are completely 180 degrees out of phase and there is cancellation of the original signal. The frequency where maximum cancellation occurs is called the ¼ wave resonant frequency, fo. Resonance nulls due to stubs in an insertion loss plot, like the one shown in Figure 1, occur at the fundamental frequency fo and at every odd harmonic thereafter.

If you know the length of the stub (in inches) and the effective dielectric constant Dkeff, the resonant frequency can be predicted with the following equation:

Equation 1

It is common practice to reduce stub lengths in high-speed backplane designs by back-drilling the stubs as close as possible to the active internal signal layer. This is a complex and costly process involving setting individual drill depths on a per board basis. Special design features must be designed into the artwork to set correct back-drill depth. Furthermore, it is difficult to verify ALL back-drilled holes were drilled correctly. I know of a case, a few years ago, where a prototype backplane was being tested, and one via had a significantly longer stub than was specified. The problem showed up by accident when the technician was characterizing the channel using a VNA and saw an unexpected resonant null in the insertion loss plot.

When all was said and done, it turned out there was a glitch in the fabricator’s software controlling the back-drilling process. There is no practical way to find these faults, short of doing VNA measurements on 100% of the back-drilled holes. With hundreds of them in a typical high-speed backplane, the cost would be prohibitive. Thus we have to trust the fabrication process of the vendor(s).

If only there were a way to terminate the stub and get rid of all this back-drilling. Well, there just might be a solution. After returning from DesignCon 2010, I was intrigued by a paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology developed by Sanmina-SCI Corporation. The company calls this technology MTSviaTM and it allows the embedding of metal thin-film or polymer thick-film resistors within a PCB stackup during fabrication. Personally, I like to call it The Stubinator. They developed this technology as an alternative to back-drilling. The beauty of this is that you can terminate all the high-speed via stubs on just one resistive layer at the bottom of the PCB.

Of course, for this to work, we need to terminate the vias with a resistance equal to the differential via impedance to be most effective. But how do we determine the via differential impedance without going through a bunch of trial and error builds? In one of my previous columns, “Practical Differential Via Modeling Made Easy,” I showed how you can model and simulate differential vias as simple twin-rod transmission line structures using simple transmission line circuit models as shown in Figure 1.

After determining fo (either by measurement of a real structure or simulating a 3D via model) and solving for Dkeff, using equation (1), the differential via impedance can be calculated using the following equation:

Equation 2

Where:

s = the center to center spacing of the viasD = drill diameter.

Example: The differential vias used in the model of Figure 1 has the following parameters:s = 0.059 in.D = 0.028 in.stub_length = 0.269 in.Dkeff = 6.14 by Equation (1) and fo = 4.4GHz Zdiff = 66 ohms by Equation (2).

By adding a 66-ohm resistor across the bottom of each via stub in the model, the blue trace in the plot shows the stub resonance has completely disappeared at the expense of an additional flat loss of about -10dB. The eye has opened up nicely.

This Stubinator technology looks like it could be a promising alternative to back-drilling. It resolves many of the issues and limitations highlighted here, as well as providing a practical solution on PCBs where back-drilling is not viable, for example, 1 mm BGA via fields. Combined with silicon that can accommodate the additional signal loading, it may extend the life of traditional copper interconnections for next-generation of Ethernet standards beyond 10 GB/s.

And, as an added benefit, Arnold won’t be back.

Bert Simonovich was born in Hamilton, ON, Canada. He received his Electronic Engineering Technology diploma from Mohawk College of Applied Arts and Technology, Hamilton, ON, Canada in 1976. Over a 32-year career, working as an Electronic Engineering Technologist at Bell Northern Research and later Nortel, in Ottawa, Canada, he helped pioneer several advanced technology solutions into products. He has held a variety of engineering, research and development positions, eventually specializing in signal integrity and backplane architecture. He is the founder of Lamsim Enterprises Inc., where he continues to provide innovative signal integrity and backplane solutions to clients as a consultant. With three patent applications and two patent grants to his name, he has also (co)authored several publications, including an award-winning DesignCon2009 paper related to PCB via modeling. His current research interests include signal integrity, high-speed characterization, and modeling of high-speed serial links associated with backplane interconnects. To contact Bert,click here.