Estimated reading time: 9 minutes

Bert's Practical Design Notes: Why Backplane Architecture is Crucial

I am often asked what I do for a living. When I say high-speed signal integrity and backplane architect, the next question is usually, “What is a backplane architect?”

According to Wiktionary, an architect is: “A person who plans, devises or contrives the achievement of a desired result.”  So by my definition, a backplane architect is any person who plans, devises or contrives the achievement of a backplane design.

Because the backplane is the key component in any system architecture, the earlier you consider the backplane’s physical architecture, the more successful the project will be. To put it into perspective, think about it in the same way as designing a building. You would never consider building it without first engaging a building architect to plan and oversee the detailed design.

Likewise, the backplane architect plans and oversees the physical backplane design before any layout is ever started. He or she works closely with a system-packaging engineer to satisfy the system requirements before any concept becomes final. Sometimes the original system architecture needs revisions due to physical limitations the backplane imposes. This can only be established with due diligence and planning during the high-level design stage.

Unlike other circuit pack designs used in the system, the backplane is analogousto the keel of a ship upon which the rest of the ship’s construction depends for support and structural integrity throughout its lifetime. Backplanes need to be right the first time, so that circuit packs can interoperate together on Day 1, and be capable of supporting future system upgrades as technology advances. Once the system has been deployed into the field, it is next to impossible to change the backplane to correct any deficiencies or to upgrade for performance like you can by redesigning the plug-in circuit packs.

The seasoned backplane architect is a unique individual usually tasked to turn the system architect’s ideas and dreams, like the system block diagram example shown in Figure 1 into reality.

Figure 1. Example of a system block diagram.

An often-misunderstood profession, backplane architects wear many hats to accomplish their goals. Often they must juggle the design requirements from many disciplines and decide on the best trade-offs for the final design. They must converse fluently with system architects, mechanical designers, circuit pack designers, connector suppliers, PCB layout designers, ASIC/FPGA and software engineers. They must be organized and meticulous in their documentation and design practice. But most importantly, they must have a sound knowledge of mechanical, PCB layout/fabrication, signal integrity, power and EMC issues.

The greatest danger in leaving the backplane design as an afterthought is the connector selection and pin-out definition. If left to system packaging engineers and board designers to define, they may not be optimum for either performance or system cost. Many times system architects and packaging engineers will merely take the total number of signals and choose a connector with the highest pin density per inch without considering PCB routing or signal integrity implications.

Inefficient routing of the traces leads to an increase in layer count and results in a thicker board. Thicker boards leads to higher hole aspect ratios and longer vias, affecting high-speed performance. Additional layer count impacts common equipment cost.

The high-level design stage is where the physical backplane architecture starts to take shape. It uncovers potential layout routing issues and gives you the confidence the design will work the first time. The importance of this stage cannot be overstated. It primarily drives these key activities:

• Sanitizing the system architecture.
• Defining the final selection of appropriate connectors.
• Defining the connector signal partitioning and circuit pack pin-outs.
• Providing the routing plan and design rules for layout.
• Defining the net topologies for signal integrity analysis and link budgeting.
• Facilitating the mechanical design of shelf and system packaging.
• Defining the minimum slot pitch for optimum routing channels.
• Facilitating early circuit pack floor planning and final card size.
• Facilitating ASIC and FPGA pin selection for optimum routing to backplane connectors.
• Estimating PCB layer count and board thickness.
• Establishing an estimate for system cost of goods to support the business case.

Proper route planning and connector pin-out definition is vital for optimum performance. When done correctly, the final schematic capture and actual PCB layout will flow smoothly with no surprises. For example, in Figure 2, the left half of the figure shows a sample of an inner layer high-level design route plan I created in Framemaker before any schematic was ever captured.

Figure 2. Example inner layer comparison of high-level design routing plan vs actual layout.

Everything was planned from the number of layers to how the tracks needed to break out of the connector fields. The right half of the figure is the actual Cadence Allegro layout showing the inner layer routing of the artwork. The due diligence done in the high-level design stage made the actual layout fairly trivial.

If you forgo this step, the worst-case scenario is: The project will need to be reset to redesign shelf mechanicals or redefine card pin-outs causing delay in meeting time to market objectives, leading to ballooning R&D costs. It’s a classic case of “pay me now or pay me later.”

The following is a list of common terms and definitions associated with system architecture and backplane design.

Backplane

A backplane is a multi-layered printed circuit board assembly serving as the backbone of a system. Its purpose is to interconnect several printed circuit board assemblies called circuit packs or cards using plug in connectors to form a complete system. These cards plug into one side of the shelf assembly.

Usually in mission critical system applications like central office telco or data centers, the backplane is passive, meaning it does not contain active semiconductor devices permanently attached as part of the final assembly. Usually connectors are the only components, but occasionally capacitors and resistors are also used. Active backplanes, on the other hand, contain active components and are often found in enterprise or consumer grade applications

Midplane

A midplane is similar to a backplane in function except that the circuit packs plug into both sides of the shelf assembly. In these systems, cards with I/O cabling from the faceplate usually plug into one side of the shelf, while non-I/O circuit pack plug in on the other side. Some midplane architectures have the front card plugged in orthogonally to the rear cards for high speed applications.

Parallel Bus Topologies

Parallel bus topologies carry data words in parallel on multiple traces from card-slot to card-slot across a backplane or from chip to chip on a circuit pack. Up until the late 1990s, most system architectures used this form of interconnect. Due to signal integrity and timing issues associated with some parallel bus backplane architectures, the speed of the bus was limited to 25-66 MHz. Two popular industry standard systems still using parallel busses today are CompactPCI and VMEbus.

The main issue with a parallel bus topology is fault tolerance where a single point of failure on the bus can bring down the entire system. Mission critical systems often had to employ redundant busses to guard against single point failures.

As performance demand increased, newer high-speed system architectures were designed using serial technology in a point-to-point or point-to-multi-point switched fabric topologies.

Switched Fabric

Switched fabric, or just plain fabric, is the term most popularly used in telecommunications and high-speed networks, including InfiniBand, Fiber Channel, PCIe, ATCA and other proprietary fabric-based architectures. In these architectures, all data passes through the fabric before continuing to its destination. It offers better total throughput than parallel busses because traffic is spread across multiple physical links. It manages and controls all functions of the network and acts as a repeater for the data flow.

Single Star Topology

The star topology is one of the most common high-speed serial topologies used in networks today. Its advantage is that it reduces the chance of network failure by connecting all of the systems to a central node. A failure of a link from any peripheral node to the central node results in the isolation of that peripheral node from all others. As a result, the rest of the systems remain unaffected.

In its simplest form, a single star topology consists of one central hub node interconnected point-to-point to other peripheral nodes resembling a spoke wheel or star configuration. When implemented in a backplane, the central node is usually the switched fabric card and the peripheral nodes are line cards. The fabric card switches messages between the other line cards in the network. The line cards usually have faceplate I/O connectors to connect to other shelves in a network.

The main disadvantage with a single star topology is high dependence of the system on the functioning of the central fabric. Failure of the fabric card can bring down the entire system. Because of this, mission critical systems employ two fabric cards for redundancy in a dual star topology configuration.

Dual Star/Multi-Star Topology

The dual-star or multi-star topology is similar to the star network topology except that it has two or more central hub nodes interconnected point-to-point to other peripheral nodes. When implemented in a backplane application, these central nodes are usually the switched fabric cards and peripheral nodes are the line cards. The additional fabric(s) provides redundancy in mission critical system applications in case of failure, or for upgrading fabric card hardware.

Fully Connected Mesh Topology

A fully connected mesh topology, when applied to a backplane application, does not have a central fabric node as in the case of star topologies. Instead, each line card node connects with all other line card nodes forming a mesh. Its major disadvantage is the number of connections grows significantly with the number of nodes. This requires additional backplane connector pins and layers to interconnect them. Because of this, it is impractical for large systems and only used when there are a small number of cards needing to be interconnected.

Bert Simonovich was born in Hamilton, ON, Canada. He received his Electronic Engineering Technology diploma from Mohawk College of Applied Arts and Technology, Hamilton, ON, Canada in 1976. Over a 32-year career, working as an Electronic Engineering Technologist at Bell Northern Research and later Nortel, in Ottawa, Canada, he helped pioneer several advanced technology solutions into products. He has held a variety of engineering, research and development positions, eventually specializing in signal integrity and backplane architecture for the last 10 years. He is the founder of Lamsim Enterprises Inc., where he continues to provide innovative signal integrity and backplane solutions to clients as a consultant. With three patent applications and two patent grants to his name, he has also (co)authored several publications, including an award winning DesignCon2009 paper related to PCB via modeling. His current research interests include signal integrity, high-speed characterization, and modeling of high-speed serial links associated with backplane interconnects. To contact Bert, click here.