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How Chip Advances Affect Packaging Processes & Materials

Advances in chip performance often require advances in electronic packaging materials and processes. I found it interesting to track the cascading cause and effect relationships of such developments. Figure 1 is an illustration of such relationships. The top driver appears to be the desire to develop faster, more powerful integrated circuits (ICs). The approach to this performance improvement of ICs is to pack more, smaller semiconductors with ever-increasing switching speed into the IC.

Figure 1: Cause and effect relationships with impact on packaging materials and processes.

These high-performance ICs require more power, which ultimately converts to heat, which needs to be dissipated. The approach taken by chip designers to reduce power requirement without lowering performance is the so-called multi-core chip architecture. My simple-minded understanding of the multicore design is that it is a more economic use of power that is supplied to the chip in the sense that chip domains that are not needed to perform a given operation go dormant and only come on when needed. (Well, I am sure there are better explanations for multi-core processors.) In any case, even with this improved design, there is a remaining need for power delivery of about 100W that features low impedance, low inductance, and low switching noise. Such power is delivered by decoupling capacitors, with high-capacitance density, ideally located very close to the chip (e.g., embedded in the package under the chip or very near the perimeter of the chip).Read the full column here.

Editor's Note: This column originally appeared in the June 2013 issue of The PCB Magazine.