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Current IssueSales: From Pitch to PO
From the first cold call to finally receiving that first purchase order, the July PCB007 Magazine breaks down some critical parts of the sales stack. To up your sales game, read on!
The Hole Truth: Via Integrity in an HDI World
From the drilled hole to registration across multiple sequential lamination cycles, to the quality of your copper plating, via reliability in an HDI world is becoming an ever-greater challenge. This month we look at “The Hole Truth,” from creating the “perfect” via to how you can assure via quality and reliability, the first time, every time.
In Pursuit of Perfection: Defect Reduction
For bare PCB board fabrication, defect reduction is a critical aspect of a company's bottom line profitability. In this issue, we examine how imaging, etching, and plating processes can provide information and insight into reducing defects and increasing yields.
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Estimated reading time: 13 minutes

Conversations with...HSIO President Jim Rathburn
Rathburn: By using thin LCP dielectric layers in the 15 to 75 micron range, we can hit a sweet spot for single ended or differential impedance tuning with much tighter tolerance and truer match with lines and spaces in the same range and maintain an aspect ratio conducive to solid copper vias. With the fusion bonding process resulting in an essentially 3D matrix of high-speed circuits and vias completely surround by a common low-dielectric constant and eliminated lossy solder mask, we have seen significant signal integrity improvements over conventional construction beyond 40 GHZ. Another big advantage is the capacitive loading effects are much easier to manage which is important for many of the low-power architectures. The fusion process also allows for embedded passive function that can be a big benefit for signal conditioning and tuning with potential SMT component reduction near the high-density regions.The graphic below shows basic design rules for single-ended circuit construction tuned with the LCP design rules. These principles are an example, and apply to differential lines as well as microstrip designs as appropriate.
You can see there is opportunity to improve the performance of existing designs with larger line and space geometries with extension to line and space reduction to improve routing capability and layer count, providing several generations of line and space reduction as the customers adopt our design rules.
Beaulieu: Can you tell us how you developed this process?Page 2 of 4
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