Cadence’s Brad Griffin Digs Deep Into DDR

Estimated reading time: 12 minutes

KD: Let's talk about your tools. Would you give us an overview of some of the advanced tools at Cadence and how you're helping designers to solve some of these higher-speed, lower-power issues?

BG: Thank you for giving me the opportunity to talk about that because we’re really excited about our products. The foundation for the PCB and IC package design technology at Cadence is Allegro technology. Allegro technology has been around a long time; it was called Valid a long time ago before Cadence acquired it. So that's been the place where all the actual physical implementation takes place. What we did is layer signal integrity and power integrity analysis tools on top of the Allegro technology, which has been in place since the mid-1990s. They’ve been serving the market fairly well, but a very exciting thing happened in 2012. Cadence acquired a company called Sigrity. Sigrity is well known for power integrity technology and their PowerDC and PowerSI tools, which enable both AC and DC power integrity analysis

When you merge that together with their signal integrity analysis technology, what we’ve been able to do is take state-of-the-art, world-class signal integrity and power integrity technology in 2012 and spent the last two and half years not only improving that technology but tightly integrating it with Allegro technology. Now the Allegro user base has grown accustomed to having tools where they can have signal integrity analysis on-the-fly right from the board. We’re giving them advanced technology that allows them to run more advanced field solvers, more advanced analysis engines and it might not sound like that much but when we go back to the idea that we only have that 300 mV swing in LPDDR4 an integrated solution is key to converging on a working solution.

We’ve got this advanced analysis technology tightly integrated with the implementation environment because what will typically happen is you’ll run an analysis and it doesn't work—it failed the JEDEC requirements. So, what do I have to do? I have to start working with my power plane, working with the signaling, cleaning up everything, maybe there are too many vias on the signal, etc. But once you do all this you rerun the analysis and see that you’re getting closer and you start to see yourself improving. Because it's so tightly integrated, our customers can accelerate the process of finding the problem, fixing the problem and verifying you fixed the problem. It's been an exciting ride the last two and half years with Sigrity and Cadence, and the Sigrity 2015 release coming out during DesignCon is really the culmination of bringing the latest and greatest technology to the market and has addressed these very difficult design and analysis challenges around LPDDR4.

KD: We have engineers and layout people—people that specifically do SI work. Are these tools used in a team application?

BG: The challenge has been that historically, data has just been thrown over the wall: I’m the designer and I throw it over the wall; the SI guy says “fix this” and throws it back over the wall, and it’s a typical back-and-forth. It's very difficult to converge. On the other hand, the work that the signal integrity and power integrity engineer performs comes from a level of expertise in his area that you can’t really expect a PCB designer to have. On the other hand, the person doing integrity analysis doesn’t really have the level of expertise to make the changes to the physical design that the PCB designer has. We recognize that, yet we try to provide an environment which allows the gap to be bridged as much as possible. So our Allegro PCB analysis tools, as I mentioned, have the signal integrity tools residing right on top, so we have an environment where the layout person with some level of knowledge—maybe he knows how to get IBIS model on the web and can attach that to one of his components and can make sure that all of his resistors and capacitors have proper values associated with the design database—can actually say let me analyze the signal and see what it looks like. He may not have the expertise to know exactly how to fix it, but at least he can identify there's a problem and then just needs to determine how to resolve it.

Our approach here is that we try to let the layout person with some level of electrical background go as far as he can and then bring the expert into the same environment. It’s how we’ve sort of structured our technology—we’ve got the base signal integrity technology that probably both expert and non-expert can use, and then we have advanced analysis technology that sits on top of that. The expert can go in and run the DDR simultaneous switching noise analysis. It can figure out that he’s going to have 64 bits simultaneously switching and the signal is not going to work. He’ll have to make some changes to the power plane to make sure it's more stable, perhaps by adding some more decoupling. He could actually, with some level of expertise about how to place things around the board, put down his own capacitors. He can then try it out, see how it’ll work and improve the overall process.

KD: Is what you're describing a radical change to front-end design with these new speeds, where it's not your classic front-end design anymore with a simple schematic passed down to a layout designer?

BG: It’s an excellent question because for quite a long time Cadence has pushed what we’ve called a constraint-driven flow, where you do a lot of analysis upfront, create constraints, drive those constraints into design and push that forward to layout and verify it at the end. That’s basically our methodology that Cadence has put in place for signal integrity, but one of the things we’re showing in our booth is that we’re moving this constraint-driven flow so it's not just signal integrity, but also power integrity. Because we believe that if the hardware engineer that is doing the schematic knows this component needs a certain amount of decoupling associated with it, instead of just putting all the decoupling capacitors on a page at the end, he basically associates his decoupling capacitors with that component in the schematic. Then when it gets to the point that you’re doing actual placement of the decoupling capacitors you’re going to get violations that tell you that you haven't placed the right capacitors within the right radius of this component. So we’re bringing this constraint-driven flow to power integrity that’s always been there for signal integrity.Page 2 of 3

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