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Solder Paste Stencil Design for Optimal QFN Yield and Reliability
April 29, 2015 | Ben Gumpert, Lockheed MartinEstimated reading time: 13 minutes
Review of the component x-rays resulted in the observation of a property that was not originally of concern, and which was only partially observed in the process yield results; solder joint consistency. When the solder paste volume is increased on the center pad, the increased standoff height results in less consistency in the perimeter pin solder joints. Figure 8 shows a typical x-ray image of a QFN68 from site B12, where the variation in solder joint volume is clearly seen, although this location passed continuity testing. A similar image from a B5 location shows much more consistent solder joints around the perimeter of the part.
By comparison, the solder joints for the QFN44 (see Figure 9) are fairly consistent regardless of component standoff.
Conclusions
Two QFN/BTC packages were installed onto representative circuit cards using a variety of solder paste applications. Many of the standard guidelines for QFN/BTC application and soldering were followed, with only the solder paste volume adjusted to control the resulting solder joint height and geometry. Actual solder joint height for this assembly was shown to correlate well to expected solder joint height according to the stencil design.
In general, an increase in the amount of solder paste used resulted in an increase in the amount of voiding. This is expected, as the pathways for volatiles to escape are reduced and the overall amount of volatiles is increased as the total solder volume increases. Voiding was low in general, with few instances of voiding exceeding 25% of the soldered area.
Thus far, the failure rates for the various solder joint configurations (height) are not as predicted by the simulation software. Of particular note is the inconsistency of the solder joints on the QFN68 packages at increased solder joint heights. The joints seen in the Figure 8 above make electrical connection, but may represent weak joints that are likely to fail relatively early. This joint variation in the previous testing could have skewed the simulation baseline, and therefore the current prediction, which likely assumes that every joint is exactly the same within the programmed parameters. Another potential impact that could be impacting thermal cycle survivability is the slight change in the solder joint shape at the toe fillet. The solder stencil was adjusted to vary the amount of solder paste applied at the perimeter pins, resulting in solder joints that had very similar geometry, but which were not exactly the same. The slightly larger solder joints on the locations with a shorter solder joint height could improve the thermal cycle survivability. The simulation software did not allow the size or shape of the toe fillet to be adjusted.
Until more failure data is collected, specific conclusions cannot be substantiated, but the observations and results so far indicate that center pad size (and presumably die to package ratio) should not be ignored when implementing QFNs. There were clear differences in the results between the two packages used in this study. Components with a small center pad are relatively robust not only in thermal cycling, but also with respect to yield and consistency in the manufacturing process. Components with a large center pad require more attention, as they have a smaller process window for optimal solder joints, and have reduced reliability. Initial results indicate that such a component is best installed with 50% or more in solder paste reduction on the center pad, but more failure data is required to determine the ideal stencil design.
Bibliography
[1] IPC-7093, Design and Assembly Process Implementation for Bottom Termination Components, March 2011
[2] Xilinx Application Note, XAPP439, (v1.0) April 11, 2005
[3] Freescale Semiconductor Application Note, AN1902, Rev. 4.0, 9/2008
[4] Cary Stubbles, “Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices”, Document No. 001-72845
[5] Atmel Application Note, “QFN Package Mounting Guidelines”, AT88RF1354, March 2009
[6] Amkor Application Note, “Application Notes for Surface Mount Assembly of Amkor’s MicroLeadFrame® (MLF®) Packages”, Rev. G., September 2008
[7] Gary Griffin, Analog Devices Application Note, “A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)”
[8] Actel Application Note, “Assembly and PCB Layout Guidelines for QFN Packages”, AC322, May 2008
[9] Ahmer Syed and WonJoon Kang, “Board Level Assembly and Reliability Considerations for QFN Type Packages”, SMTA International, September 2003
[10] Tong Yan Tee, Hun Shen Ng, Jean-Luc Diot, Giovanni Frezza, Roberto Tiziani, and Giancarlo Santospirito, “Comprehensive Design Analysis of QFN and PowerQFN Packages for Enhanced Board Level Solder Joint Reliability”, Electronic Components and Technology Conference, San Diego. CA. May 2002
[11] Pamela O’Brien, Thomas Koschmieder, “Quad Flat Pack No Lead (QFN) Board Level Reliability Study for Automotive Applications”, SMTA International, 2003
[12] Dong Hyun Kim, Mudasir Ahmad, Sue Teng, “Reliability Study and AF Modeling for SnAgCu Solder Joints and SnPb Solder Joints in QFN Packages”, SMTA Journal, Volume 23 Issue 1, pp. 11-17
[13] Scott Nelson, “Bottom Termination Component Land Pattern Design and Assembly for High Reliability Electronic Systems”, SMTA Journal, Volume 25 Issue 4, 2012, pp. 23-31
Editor's Note: Originally presented at the IPC APEX EXPO Technical Conference Proceedings.
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