Solder Paste Stencil Design for Optimal QFN Yield and Reliability

Estimated reading time: 13 minutes

One assembly was cross-sectioned to evaluate solder joint heights, and the rest were subjected to thermal cycling. The assemblies were continuously electrically monitored during testing to identify when component failures occur. An air-circulating environmental chamber and a thermal cycle of -55°C to 125°C were used. The chamber includes a continuous recording unit for temperature. The ramp rate was set to 4.5°C/min and the dwell time set to 15 minutes.

An electrical continuity monitor was used determine time of failure for individual components. Testing was performed in accordance with IPC-SM-785 standard, with failures identified as short duration, high resistance spikes as described in section 4.3.1 of that guideline. Variations in channel current-loop resistance which exceed the selected threshold resistance were flagged as events, subject to the minimum event duration limit.

Results

Thirteen cards were built with a total of 20 QFN44 and 28 QFN68 packages on each card. Table 2 shows results from cross-section measurements, x-ray inspection, and continuity check. Several points are evident from these results. The first is that ‘open’ defects were present in the QFN68 locations where the least amount of solder reduction was applied. The QFN44 package did not exhibit any of these open defects. Bridging was not a common problem, but seems to have occurred randomly.

Voiding levels were fairly low. Only three locations had total voiding above 25%, and some of these were attributed to ‘bottoming-out’ of the component on the solder mask at B1 sites. It was determined that the solder volume at these sites was low enough such that some parts were resting on the solder mask, which enabled voids to remain in the solder joint instead of making their way out.

One test board was selected for cross-sectioning to evaluate solder joint heights and geometry. Figures 4 and 5 are representative images of the solder joints formed. On components with a larger stand-off height (i.e. taller solder joints), the solder at the toe is slightly concave in shape, while it is convex on the parts with a lower stand-off. This demonstrates that the sizing of the stencil apertures at the perimeter pin locations was not quite compensated enough to achieve consistent fillets at all locations. Solder joint open defects were reworked by hand and were tied in for thermal cycle testing, although the locations were noted for future reference to determine the impact that rework may have on reliability.

Solder joint height for the QFN package is generally defined by the amount of solder applied to the center pad. In this study, the PCBs used had a HASL finish, so they have some volume of solder already present on the center pad. Cross section measurements of the solder joint height (actual height) were compared to the expected values at each location, as seen in Figure 6. This data demonstrates a good trend, and variation seen is attributed to three main variables; pre-existing solder volume from HASL, solder volume applied in-process, and variation of the QFN position in the cross-section (i.e. potential tilt of the package).

To date, the test vehicles have been exposed to 1100+ thermal cycles (-55°C to 125°C), with the profile as shown in Figure 7. There have been only four failures out of the 576 locations thus far. These failures have each been from a QFN68 package of a unique site, but none of these sites were those with greater than 50% solder reduction (the standard lower limit for paste application.)

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