-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueProper Floor Planning
Floor planning decisions can make or break performance, manufacturability, and timelines. This month’s contributors weigh in with their best practices for proper floor planning and specific strategies to get it right.
Showing Some Constraint
A strong design constraint strategy carefully balances a wide range of electrical and manufacturing trade-offs. This month, we explore the key requirements, common challenges, and best practices behind building an effective constraint strategy.
All About That Route
Most designers favor manual routing, but today's interactive autorouters may be changing designers' minds by allowing users more direct control. In this issue, our expert contributors discuss a variety of manual and autorouting strategies.
- Articles
- Columns
- Links
- Media kit
||| MENU - design007 Magazine
Cadence Unveils Sigrity 2016 Technology Portfolio
January 21, 2016 | PRNewswireEstimated reading time: 2 minutes
Cadence Design Systems, Inc., has unveiled the Sigrity 2016 technology portfolio, which improves product creation time with an enhanced PCB design and analysis methodology that is ideal for multi-gigabit interfaces.
To speed up the qualification of a physical design for the USB Implementers Forum (USB-IF) compliance test, the Cadence® Sigrity technology portfolio includes automated support for IBIS-AMI model creation, fast and accurate channel model extraction using multiple field solvers, and an automated power-aware signal integrity analysis report to validate a virtual USB 3.1 channel. These technologies, when used together, can shave weeks off the design process.
Previously, IBIS-AMI model creation has been a manual process. The Sigrity 2016 technology portfolio now leverages validated equalization algorithms used by the Cadence Design IP SerDes PHY team and provides an automated methodology for combining, paramaterizing and compiling the algorithms into an executable model. This can increase the pool of engineers capable of efficiently developing SerDes I/O models.
The new "cut and stitch" technology features the ability to create accurate channel models ten times faster by using a mix of hybrid and 3D full-wave field solvers. With minimal manual intervention, the serial link channel can be divided into sections, solved for and automatically stitched together into a single interconnect model. The rapid model extraction technique enables engineers to trade-off various signal routing and layer transition strategies and still meet demanding time-to-market requirements.
Other capabilities that have been enhanced in the portfolio are:
- New quasi-static 3D field solver integrated with 3D full wave and hybrid solver technology available for both IC package and PCB analysis
- Electrical Performance Assessment integrated directly into the IC Package Designer's layout environment
- Optimized decoupling capacitor schemes updated to Allegro® PCB layout
- Improved Power Integrity analysis methodology for PCB designers
To learn more about Sigrity solutions, click here.
"The Sigrity 2016 portfolio features capabilities that increase efficiency and speed up the design process by enabling designers to qualify multi-gigabit standard interfaces such as USB 3.1," said Vinod Kariat, vice president of Custom IC and PCB Group R&D at Cadence. "These features remove the need to manually write and compile code using a software development environment to create SerDes I/O models and that makes modeling of transceivers and interconnects faster."
"Our collaboration with Cadence has allowed both engineering teams to develop tools that can improve our joint customers' product creation process. The Sigrity 2016 release aligns with our customers' needs to address serial link analysis challenges as early as possible," said Brian Reich, General Manager Performance Oscilloscopes, Tektronix. "Together we can help our joint customers reduce weeks from their design cycles as they prototype USB 3.1 interfaces with the Sigrity solution and validate them in the lab with the Tektronix solutions."
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Testimonial
"We’re proud to call I-Connect007 a trusted partner. Their innovative approach and industry insight made our podcast collaboration a success by connecting us with the right audience and delivering real results."
Julia McCaffrey - NCAB GroupSuggested Items
Coming Soon: The Advanced Electronics Packaging Digest
08/27/2025 | Marcy LaRont, I-Connect007The upcoming Advanced Electronics Packaging Digest is a curated, condensed monthly publication designed to keep you informed and engaged with the fast-moving world of advanced electronics packaging (AEP). In our inaugural September issue, we will begin at the foundation with an in-depth interview featuring Matt Kelly, CTO of the Global Electronics Association. Kelly and his Technology Solutions Team approach advanced packaging from a holistic systems perspective.
Nordson Reports Q3 Fiscal 2025 Results and Updates Full Year Guidance
08/21/2025 | BUSINESS WIRENordson Corporation reported results for the fiscal third quarter ended July 31, 2025. Sales were $742 million compared to the prior year’s third quarter sales of $662 million.
Haylo Labs Acquires Plessey Semiconductors
08/20/2025 | Haylo LabsHaylo Labs has acquired Plessey Semiconductors, the UK’s leading innovator in microLED display technology.
SoftBank Group and Intel Corporation Sign $2B Investment Agreement
08/19/2025 | Intel CorporationSoftBank Group Corp. and Intel Corporation today announced their signing of a definitive securities purchase agreement, under which SoftBank will make a $2 billion investment in Intel common stock.
20 Years of Center Nanoelectronic Technologies (CNT) – Backbone of German Semiconductor Research Celebrates Anniversary
08/14/2025 | Fraunhofer IPMSThe Center Nanoelectronic Technologies (CNT) of the Fraunhofer Institute for Photonic Microsystems (IPMS) is celebrating its 20th anniversary this year. Since its founding in 2005, it has developed into a pillar of applied semiconductor research in Germany and Europe. With its unique research cleanroom and equipment adhering to the 300-mm wafer industry standard, CNT is unparalleled in Germany and serves as a central innovation driver for the microelectronics industry.