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ICD Adds Matched Delay Optimization to Stackup Planner
June 20, 2016 | ICDEstimated reading time: 1 minute
In-Circuit Design Pty Ltd (ICD), Australia, developer of the ICD Stackup and PDN Planner software, has released a Matched Delay Optimization feature for the Stackup Planner.
Signals propagate at the speed-of-light in free space. However, this speed varies dramatically depending on the surrounding dielectric materials. Each layer, of a multilayer PCB, can have a very different propagation speed. This is particularly important for the latest high-speed DDR3/4 memory devices. The new “Matched Delay Optimization” feature, of the ICD Stackup Planner, allows you to not only match the length of busses, but takes this one step further by automatically calculating the appropriate length required to match the delay exactly. The integrated field solver simulates the flight time, of each signal layer, to quickly give you the results you need to effectively route memory.
“A matched length of 2.3 inches for a DDR3/4 Data lane can produce up to 70ps delta, between signal layers, leaving the timing way outside the required DDR3/4 setup and hold times,” said Barry Olney, CEO. “Designers need to pay strict attention to the signal propagation, on each layer, ensuring the total flight time of the critical signals match, regardless of length. The ICD Stackup Planner now allows you to optimize this delay."
The relative signal propagation is displayed as a bar graph, once the matched length has been set. Selecting “Matched Delay” automatically optimizes the length, of each signal layer, to match the maximum delay. The user can then route the data lane, to the exact delay, in their preferred design tool.
About In-Circuit Design Pty Ltd
In-Circuit Design Pty Ltd, based in Australia, developer of the ICD Stackup and PDN Planner software, is a PCB Design Service Bureau and specialist in board level simulation. Visit www.icd.com.au.
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