Knocking Down the Bone Pile: Solderability Test Methods, Myths, and Realities
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Zestron's Jigar Patel to Present at IPC APEX EXPO
January 15, 2020 | ZESTRONEstimated reading time: Less than a minute
ZESTRON, the global leading provider of high precision cleaning products, services, and training solutions in the electronics manufacturing and semiconductor industries, is pleased to announce that Jigar Patel, M.S.Ch.E., Senior Application Engineer, will present “Solder Mask and Low Standoff Component Cleaning—A Connection?” at IPC APEX Expo 2020 in San Diego, CA.
Introduction: Today, printed circuit boards used within electronic assemblies for high reliability applications are typically subjected to cleaning or defluxing processes. As assembly complexity has increased, that is, more densely populated with greater use of stacked and leadless components and with ever reducing standoff heights, effective defluxing is increasingly challenged.
The author’s purpose in conducting this study was to assess the under-component cleanliness as impacted by different solder mask options which are used to protect the copper traces and pads integral to PCB design. The solder mask specifications used in this study included: Solder Mask Defined (SMD) and Non-Solder Mask Defined (NSMD). No Solder Mask (NoSM) was also tested for comparative purposes.
Jigar Patel will present the Design of Experiment and key results during the Cleaning track on Thursday, February 6th, from 9:00 AM to 10:00 AM. For more information, please visit www.ipcapexexpo.org.
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