Real Time with… SMTAI 2020: Technical Conference Review

Estimated reading time: 16 minutes

SMTAI 2020, which was converted to a virtual event, took place from September 28–30. I attend every year, but since there was no keynote in the virtual format, I went straight to the technical conference. This event covered a broad range of topics related to everything in assembly. Over 90 technical presentations are available, but this report covers just some of the sessions I attended.

Hiroshi Komatsu, Connectec Japan Corporation

#150: 10-Micron Pitch Wiring and Bump on Substrate Formed by Imprinting Technology to Apply Low-Temperature Flip-Chip Bonding for Low-Temperature Bonding, and Fine-Pitch, Imprinting, CTE

The theme of this presentation was a new process for the minimum bump pitch in flip-chip bonding. It is limited by the difference in expansion or shrinkage caused by the CTE mismatch between the chip and the substrate. It has been exceedingly difficult to achieve a bonding pitch of 35 microns or less in the conventional technology using solder.

Due to this technical limitation, the integration of hetero-chips with a large number of pin count on a substrate was intensively studied using 2.5D LSIs that typically use an interposer, which stacks chips three-dimensionally using a through-silicon via (TSV). However, the manufacturing technology, such as a silicon interposer and TSV used for these 2.5D LSIs, is an expensive process.

In this study, Komatsu reported a narrow-pitch bonding technology based on low-temperature flip-chip bonding using silver conductive paste as bumps. In this technology, a conductive paste was used to simultaneously form wiring and bump with the pitch of 10 microns on the substrate by using an imprinting method and non-conductive paste dispensing, followed by flip-chip bonding and curing at 140°C to enhance the bonding strength and reduce the resistance of the conductive paste. This allows the use of organic substrates like polyimide and PET film.

To form wiring and bump with the pitch of 10 microns simultaneously on the substrate, the final wiring and bump shape is formed in advance as a master mold, and this is transferred to a replica mold to form an inverted shape. Further, a conductive paste is filled in the concavity of the replica mold and then transferred to the substrate. Three examples were shown using an organic substrate and the low-temperature bonding technique that otherwise could not be applied to packages.

Figure 1: Low-temperature FCB IoT application.

Figure 2: Low-temperature FCB process flow.

Charles Woychik, i3 Microsystems Inc.
#151: 3D Integration Using Heterogeneous System-in-Package (HSiP) Technology FOWLP, Reconstituted Wafers, Multi-Chip Module, Embedded Die

An interposer with embedded semiconductor dies and passive devices has been fabricated using a heterogeneous system-in-package (HSiP) technology to create a highly dense integrated multi-chip module (MCM) package solution. This technology is based on fan-out wafer-level packaging (FOWLP) technology, which consists of a molded core wafer having embedded devices, through mold vias (TMVs), and passive devices, along with buildup circuitry layers on both sides of the molded core wafer.

This HSIP technology can integrate multiple die and passives to achieve maximum device packing, which is molded using an epoxy-based silica filled molding compound to create a reconstituted wafer. To maintain a flat module, it is necessary to balance the amount of Cu in both the front and back layers to achieve the neutrality of the module bow during thermal excursions. To create the buildup layers, a first dielectric material is deposited over the reconstituted wafer, vias are created, and then the Cu circuitry is formed. This new process was provided in detail.

This sequential process is repeated until the required number of layers is formed. This same process is repeated on the backside of the wafer. After the buildup layers are produced on the molded wafer, the individual modules are diced out of the wafer. On both sides of the outer layers are ball-grid array (BGA) pads, which allow these modules to be stacked using conventional solder attach methods. Reliability testing was conducted on the new HSIP of 1,000 thermal cycles, including 0–100°C and -40–125°C.

Figure 3: The future is stacked FOWLP.

Figure 4: Test vehicle design, single slice.Page 1 of 7

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