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AltiumLive 2022: Power and Signal Integrity—Return to SenderFebruary 23, 2022 | Andy Shaughnessy, Design007 Magazine
Estimated reading time: 9 minutes
I recently spoke with Heidi Barnes and Stephen Slater, both engineers with Keysight Technologies, about their presentations at this year’s virtual AltiumLive. They discussed ways to avoid signal and power integrity challenges later by following simple board design practices early on, how SI and PI are interconnected, and why the return path must be more than an afterthought in high-speed designs.
Andy Shaughnessy: Welcome. Good to see you all, even virtually.
Stephen Slater: Thanks, Andy. Nice to meet you.
Heidi Barnes: Good to see you again.
Shaughnessy: Tell me about your presentations. How about ladies first?
Barnes: Well, it’s an interesting question: What comes first? Power integrity or signal integrity? It’s kind of like the chicken or the egg, because you can’t have a signal without power, and yet it’s the signal that defines what power you need. They both are very intertwined, and they often share the same ground return. It’s a very complex problem when you start looking at power integrity and signal integrity and how they all play together.
The title of my paper is “What is Target Impedance and Why is Power Delivery AC, not DC?” The main reason I’m doing this presentation, especially for the Altium layout designers, as well as hardware engineers, is they really need to understand that power delivery is not a DC problem - it’s actually AC.
Digital loads are very dynamic, switching loads. With power delivery, we need to start looking at how it behaves over frequency. In doing that, you realize how important it is to capture the PCB parasitics. The layout and how you do your stackups can have a very big impact on how well your power is delivered. How quiet is that power? Is it noisy? I’m doing a lot of power integrity basics, but I’m going to talk about how analyzing in the frequency domain can give you a lot of insights and then lead to really good time domain, quiet power delivery; and also look at how to do EM model simulations for the printed circuit board.
Shaughnessy: What are some of the more common mistakes that you see designers committing, as far as power integrity?
Barnes: One of the biggest mistakes is not accounting for PCB parasitics, the inductance in the path of the power delivery—whether it’s inductance of a component, inductance in the printed circuit board, or inductance in your vias that are interconnecting things. I want to provide a better understanding of how that layout can impact the delivery of power to the load.
Also, simulations are great, but we need to verify that the models we’re using for different components are accurate. That’s another part of power integrity basics: learning where those models come from and how to put things together to do a PI ecosystem simulation.
Shaughnessy: What do you hope the attendees take away from your class?
Barnes: I’m hoping to drive home that power integrity simulations are actually pretty easy. I have a three-step workflow that I talk about: start with DC IR voltage drop, copy that to an AC simulation to look at the impedance vs. frequency, then bring that EM model into a schematic—sort of a spike-type schematic simulation. Then you can run a full PI ecosystem, transient time domain simulation and look at power rail ripple. It is not a difficult workflow methodology and I’m hoping to encourage more engineers and designers to take a look at simulation and avoid late-in-the-design failures.
Shaughnessy: Right. It does seem like designers discovered power integrity later than signal integrity. I guess they had their hands full for so long with signal integrity.
Barnes: Yes. One of my most favorite examples in history is the transatlantic cable for the telephone. The first time they ran the transatlantic cable across the Atlantic, it wasn’t working right, and the performance was rapidly degrading. An engineer, if he was an engineer, said, “Oh, all you have to do is crank up the voltage.” Well, they turned up the voltage so far they burned it up because they didn’t understand transmission line theory of mismatched impedances. They didn’t have an SI engineer back then.
In a similar light, I look at power integrity designs and ask, “What are you doing with factor of 10 decoupling capacitors that you just used from somebody’s datasheet?” If you have factor of 10 capacitors on your design, then you didn’t design the decoupling capacitors. Where’s the power integrity engineer? Are you going to just blindly use somebody else’s design and then just throw more capacitors at it if you have a problem? That’s my encouragement, a little bit of simulation and knowledge can go a long way to lowering costs, improving designs, and mitigating late in the design failures.
Shaughnessy: Stephen, tell me about your class.
Slater: Actually, that’s a nice segue, because over into the signal integrity domain, you have a lot of design constraints that are passed on to the PCB designer from a chip, for instance, “For these high-speed digital traces, these are some of the things you need to do.” The routing has to be a certain width, certain spacing, certain impedance tolerance. This is the way we expect the delay of the signals to be within this maximum amount of skew.
But for the PCB designer, you’re taking these as inputs and trying to route signal nets properly without having much experience as to how those things are impacting the signal integrity. That’s what we try to do in my course. To get a feel for what’s in it, we’re going to take an example of a high-speed digital differential pair at 16 gigabit per second, and we’re going to vary a bunch of design parameters, like on the via design: How does the drill size or the anti-pad size or the catch pads affect the performance of the via?
We’re going to look at things like surface roughness for the signal traces. We’re also going to look at impedance mismatch, what impact that’s going to have on the eye diagram; and give the users, the participants, a feeling for what controls they have over those specific parameters. For instance, if my impedance is too low, what do I do? We provide attendees with an idea about what the equivalent circuit model would look like, and then provide them with a feel for how capacitance and inductance impact impedance. When we know this, if our transmission line is a bit too low in impedance, then we have an idea about what we can do to control it, change it, and make it higher.
To end the presentation, we show the difference between a nominal design and a fully optimized design to see how much this buys us. The simulation analysis tools we use here are very, very simple and easy to use. It can be done for pre-layout analysis before you start the physical layout design, but once you’ve already completed the physical layout design, the workflow then goes on to verify that what you laid out, is going to work and perform at the data rates we care about.
Shaughnessy: Well, that’s great. It sounds like you’re explaining this for PCB designers, not necessarily just people who have a Ph.D. in electrical engineering.
Slater: Yes. In fact, when it comes to things like via design, I think not all PCB designers have a full grasp on quantifying the ground stitching vias—where you place them, how many you place, and what impact they have on the impedance of this differential via.
In this simulation tool, we just parameterize where those stitching vias are placed and the separation distance. You just sweep it, let it run, it gives you the different simulation results, and we can quickly compare them. In fact, that’s the optimization process; you find things you have control over, and which way steers the impedance. Then we try and match it better. We turn some of the controls until we can get something that’s matched to the desired impedance for this PCI Express set of traces.
Shaughnessy: All right. What are the big takeaways from your class, Stephen?
Slater: I think there’s the educational aspect of knowing, let’s say, some of the design parameters that you have control over, what it actually does to the impedance. Knowing those relationships is a pretty big takeaway. Second, would be that there are easy to use analysis tools the designer can get into to predict and optimize the design before committing the board to manufacture.
Shaughnessy: This question is for both of you: Since we are seeing young people once more coming into the field, what advice would you give them as far as power integrity and signal integrity?
Barnes: There’s the classic DesignCon response from Bruce Archambeault: The ground is for potatoes and carrots. In the world of signal integrity and power integrity, we have return paths. It’s frustrating to see a schematic that just throws a little ground symbol here and there and hides the complexity of how that simple little ground symbol is interconnecting everything on your board. All signals must have a return path.
When you’re laying out a board or thinking about a design, or even in a schematic, ask yourself, “Where is that return path?” When you’re looking at where a signal is routing, don’t just look at the signal trace. Ask, “Where’s the nearest ground? How is that signal constantly returning back to the source?” This way, you are controlling that impedance either in terms of signal integrity or in power integrity. In power integrity we worry about the loop inductance, because any inductance in the path is creating a higher impedance with frequency, and you have to compensate that inductance with more capacitance.
If the inductance is impeding the delivery of power to my load and I have to compensate for that with a capacitor that can provide the charge delivery. Even though the inductance is increasing the impedance, the capacitor decreases it. In summary, if you’re new to print circuit board layout and electronic design, really pay attention to how that return path is working.
Shaughnessy: Great. Stephen?
Slater: I think I’ll give a little career advice. For anyone coming out of university and trying to get into the industry, I suggest spending as much time as you can on industry standard tools really helps you to add value to the company as quickly as possible. I’ve noticed university students who had internships and spent time on certain application domains using industry standard tools were highly valued as soon as they graduated. They can be put to work immediately on very useful analyses and investigations. That’s my key advice. Try your best to broaden your horizons, get access to as many different tools as you can, and build up your proficiency.
Shaughnessy: Great. I appreciate your time. Thank you both.
Barnes: Thank you, Andy.
Watch both Heidi Barnes's presentation "What is Target Z and Why is Power Delivery AC Not DC?" and Stephen Slater's presentation "The Keys to Simulating and Optimizing High Speed Interfaces" below.
Siemens, TSMC Collaborate to Help Mutual Customers Optimize Designs Using Foundry's Newest Advancements09/29/2023 | Siemens
Siemens Digital Industries Software announced new certifications and collaborations with longtime partner TSMC, resulting in the successful qualification of multiple industry-leading Siemens EDA product lines for the foundry’s latest process technologies.
Cadence Design Systems, Inc. announced the availability of new system prototyping flows based on the Cadence® Integrity™ 3D-IC Platform that support the 3Dblox 2.0 standard.
TSMC announced the new 3Dblox 2.0 open standard and major achievements of its Open Innovation Platform (OIP) 3DFabric Alliance at the TSMC 2023 OIP Ecosystem Forum.
Keysight Technologies, Inc., Synopsys, Inc., and Ansys announced a new reference flow for the TSMC N4PRF, the world's leading semiconductor foundry's advanced 4 nanometer (nm) radio frequency (RF) FinFET process technology.
Rigid-flex circuits are unique structures; part rigid board and part flex, they’re increasingly working their way into many of the electronic devices we use every day. There have been many advances in rigid-flex lately as more companies find themselves exploring this technology. So, before I started writing this article about rigid-flex design, I double-checked a few things. Fortunately, there is plenty of rigid-flex information available on a variety of great websites that we all know and trust.