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Q&A: The Learning Curve for Ultra HDIOctober 20, 2022 | Andy Shaughnessy, Design007 Magazine
Estimated reading time: 2 minutes
For this issue on ultra HDI, we reached out to Tara Dunn at Averatek with some specific questions about how she defines UDHI, more about the company’s patented semi-additive process, and what really sets ultra HDI apart from everything else. Do designers want to learn a new technology? What about fabricators? We hope this interview answers some of those questions that you may be having about these capabilities and what it could mean for your designs.
Q: How do you define ultra HDI? What is the cutoff in mils or microns?
A: That is an excellent question. At this point I think it means different things to different people depending on where their current HDI capabilities are. IPC has created an ultra HDI working group and I believe the definition they are working with is that to be considered ultra-HDI, a design needs to include one or more of these parameters: Line width below 50 µm, spacing below 50 µm, dielectric thickness below 50 µm, and microvia diameter below 75 µm.
Q: Averatek has developed the A-SAP™ semi-additive process, which can produce traces down into the UHDI space. Can you clear up the differences between mSAP and A-SAP, and what this means to designers and design engineers?
A: In general, SAP, or a semi-additive process, is a process that starts with a very thin layer of copper and then builds the trace patterns from there. One common differentiating factor in these two approaches to SAP is the starting copper thickness. Typically, copper thickness that is 1.5 microns or above would be considered mSAP, or a modified semi-additive process. Because the copper is a little thicker than other SAP processes, it requires more etching, which can have impacts on trace width and space and also the sidewalls of the trace. This process can typically provide features as small as 30 microns in highly specialized facilities that are running extremely high-volume manufacturing. This technology is commonly seen in our smartphones.
Averatek’s A-SAP begins with a much thinner electroless copper, typically 0.2 µm and this copper thickness, or thinness if you will, enables the fabricator to produce much finer feature sizes. The technology is capable of traces and spaces as small as 1 micron if the fabricator has advanced imaging equipment. Typically, PCB fabricators have equipment that can image traces to 12.5 µm today. There are also signal integrity benefits to this process. Because the base copper is so thin, there is minimal impact on the trace sidewalls, and greater control to line width resulting in impedance control tolerance improvements.
One other difference between the mSAP and A-SAP technologies is in the ratio of trace height to trace width; mSAP processes allow a 1:1 ratio of height to width and A-SAP traces can be produced with aspect ratio of 2:1 or greater. For example, a 25 µm wide trace could be 40 µm tall. This has gotten a lot of attention from a signal integrity perspective.
To read this entire article, which appeared in the October 2022 issue of Design007 Magazine, click here.
The "Global Copper Clad Laminates Market (by Type, Application, Reinforcement Material, & Region): Insights and Forecast with Potential Impact of COVID-19 (2023-2028)" report has been added to ResearchAndMarkets.com's offering.
The SCHMID Group, a global solution provider for the high-tech electronics, photovoltaics, glass and energy systems industries, will be exhibiting at productronica in Munich from November 14 – 17, 2023.
The topic of intrinsic copper structure has been largely neglected in discussions regarding the PCB fabrication quality control process. At face value, this seems especially strange considering that copper has been the primary conductor in all wiring boards and substrates since they were first invented. IPC and other standards almost exclusively address copper thickness with some mild attention being paid to surface structure for signal loss-mitigation/coarse properties.
At PCB West, I sat down for an interview with John Andresakis, the director of business development for Quantic Ohmega. I asked John to update us on the company’s newest materials, trends in advanced materials, and the integration of Ticer Technologies, which Quantic acquired in 2021. As John explains, much of the excitement in materials focuses on laminates with lower and lower dielectric constants.
Printed circuit board (PCB) reliability testing is generally performed by exposing the board to various mechanical, electrical, and/or thermal stimuli delineated by IPC standards, and then evaluating any resulting failure modes. Thermal shock testing is one type of reliability test that involves repeatedly exposing the PCB test board to a 288°C pot of molten solder for a specific time (typically 10 seconds) and measuring the number of cycles it takes for a board’s copper layer to separate from the organic dielectric layer. If there is no delamination, fabricators can rest assured that the board will perform within expected temperature tolerances in the real world.