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EIPC Review: Ultra-high-density Interconnects, Thin-film Resistor MaterialsMay 10, 2023 | Pete Starkey, I-Connect007
Estimated reading time: 6 minutes
It’s been a little while since I first had the opportunity to review an EIPC Technical Snapshot webinar. This excellent series began in October 2020 when our industry was besieged by the COVID-19 pandemic. It has continued successfully as restrictions have lifted and provides an effective channel for the efficient sharing of relevant knowledge that complements the traditional live conferences. The 20th in the series, in December 2022, focused on environmental issues impacting the electronics industry. In early February, EIPC held its live Winter Conference in Lyon and now, by popular demand, the 21st Technical Snapshot fills a slot before the Summer Conference scheduled for mid-June in Munich.
The webinar on May 3 was introduced and moderated by EIPC technical director Tarja Rapala-Virtanen. Her first presenter was John Johnson, director of business development at American Standard Circuits, with a detailed case history of ASC’s successful realisation of ultra-high-density interconnects.
Reviewing changes in the global electronics market, Johnson commented that the world geopolitical situation has shifted the focus for critical PCBs and package substrates back to the West, although the capability of most North American fabricators is limited to 75-micron line-and-space technology achieved by subtractive processing. There is an increasing demand for ultra-high-density interconnection solutions but most of the industry is not prepared for the revolutionary change this will require.
American Standard Circuits considered several options before establishing its ultra-high-density capability. The company believed that modified semi-additive processing (m-SAP) using thin-foil laminate would be capital-intensive, with risks of yield loss and a practical line-space limit around 25-30 microns. They saw additive plate-up technology as a less capital-intensive option that would be easily adapted to sub-25 microns and thus provide a meaningful path toward ultra-high-density interconnects and packaging substrates. Consequently, they licensed the proprietary A-SAP process offered by Averatek, the key component of which is a solvent-based “liquid metal ink” that puts down a very thin but very dense catalyst layer. This enables a coherent electroless copper deposit at thicknesses as low as 0.1 micron, with good adhesion to the substrate, that can be used as a base for copper pattern electroplating and subsequently flash-etched with no need for etch resist and minimal sidewall attack on the conductor pattern. Very fine conductor geometries can be achieved.
Johnson used graphical examples to demonstrate the circuit density improvements that can be realised as line-space dimensions are reduced. Compared with typical 75-micron technology, 25 micron would result in a 9x increase and 12.5 micron in 36-times. For the most part, American Standard Circuits’ existing equipment and processes gives them 20-micron capability. Their objective is to extend this to 10 microns within 12 months, for which they require enhanced imaging and optical inspection facilities.
He summarised the process sequence: Unclad substrate, followed by coating with liquid metal ink, deposit electroless copper, apply photoresist, expose and develop image, electroplate copper, strip photoresist, and flash etch.
His microsection examples showed the geometry of high-aspect-ratio 11 micron conductors before and after flash etching, indicating vertical sidewalls and negligible loss of width. These characteristics offer benefits in reduced insertion loss and improved inductive and capacitive coupling of differential lines. He referred to published work by Eric Bogatin on the topic.
Johnson explained that A-SAP technology enables the use of very thin dielectrics and is compatible with a wide range of ultra-high-speed, low-loss substrates, even those which are difficult to manufacture as ultra-thin-foil copper-clad materials for m-SAP applications. High peel strengths are consistently achieved with A-SAP processing, even on PTFE. He gave examples of high-density demonstrator patterns in multilayer constructions and commented that the process tends to remove stress from individual layers, benefiting layer-to-layer registration. Further examples showed 4-mil diameter copper-filled vias on 4-mil thick layers, and a current project at American Standard Circuits features lines and spaces at the 20 micron level.
Tarja Rapala-Virtanen thanked Johnson for sharing some secrets of ultra-fine-line high-density PCBs before introducing John Andresakis, director of business development at Quantic Ohmega, who delivered a presentation entitled, “Thin Film Resistor Materials for High Performance Electronics.”
Andresakis, well-known as a leading expert in embedded passive components, began by explaining the structure and history of the Quantic Electronics group, of which Quantic Ohmega is a specialist division with more than 50 years’ experience as an embedded resistor innovator. He described how thin film resistive materials can be applied in high-reliability design applications, not only to replace discrete surface mount resistors by embedding the resistors in the printed circuit board, enabling miniaturisation, weight reduction and improved signal integrity, but also as localised heaters and microwave absorbers.
He explained that resistive foils are manufactured in a roll-to-roll format as a thin-film metal alloy/copper foil combination known as a resistor-conductor material or RCM. The RCM can be laminated to a wide range of dielectric substrates, like regular copper foil but with the resistive side against the dielectric, and subtractively processed to produce copper circuits and planar resistors. The resistive layer may be electrodeposited non-magnetic nickel-phosphorus or vacuum deposited non-magnetic nickel-chromium, nickel-chromium-aluminium-silicon, or chromium-silicon monoxide alloys. It is available in a wide range of sheet resistivities.
Sheet resistivity is measured in ohms per square, and Andresakis took time to explain the terminology, why the value is dimensionless and how to incorporate various resistor values into a design using a single material by specifying area and length-to-width ratio of individual components.
He described the process sequence for fabricating inner layers with thin-film resistors by two-stage photoimaging and two- or three-stage subtractive etching, depending on the resistive material. After defining the combined conductor-resistor image by normal photomechanical processing, the unwanted copper is etched with cupric chloride, which will also remove vacuum-deposited nickel-chromium. Other resistive alloys may require an additional etching step using copper sulphate. Once the combined conductor-resistor pattern has been fully defined, the first-stage photoresist is stripped and the photomechanical process repeated to define the areas of copper conductor to be removed to reveal the required resistor image. An alkaline etch then removes the unwanted copper without attacking the resistive film, followed by a final stripping of the photoresist.
Andresakis mentioned that resistor calculators and design guidelines are available, together with comprehensive simulation parameters for use in modelling tools, characteristic values for shifts in ohmic value after high temperature lamination, power ratings, and tolerances. He summarised the performance benefits of thin-film resistor foil: reduced parasitic capacitance and inductance compared to surface mount components, reduced metal-to-metal transitions associated with chip resistors, and fewer vias on critical nets, enabling improvements in electrical properties as well as freeing up available space.
Current areas of development include 3- and 5-micron carrier foils and lower-profile copper. Thin-film resistor foil technology is being used with build-up films for applications in chip packaging and interposers. A significant advanced application is in MEMs microphones for smart phones. The ability of thin film resistive materials to absorb electromagnetic waves gives many opportunities for applications in radar systems. They can also be used in the fabrication of resistive cards, high impedance surfaces, and frequency selective surfaces, with excellent long-term reliability for mission-critical applications. Quantic Ohmega has partnered with leading OEMs to understand market trends and technical needs. “It’s really up to the imagination of designers as to how to use these materials,” he said.
After moderating a lively Q&A session, Rapala-Virtanen wrapped up the proceedings and thanked all who had taken part in another excellent Technical Snapshot event. She reminded participants that the EIPC Summer Conference will be held in Munich, June 15–16. Find the details at eipc.org.
The "Global Copper Clad Laminates Market (by Type, Application, Reinforcement Material, & Region): Insights and Forecast with Potential Impact of COVID-19 (2023-2028)" report has been added to ResearchAndMarkets.com's offering.
The SCHMID Group, a global solution provider for the high-tech electronics, photovoltaics, glass and energy systems industries, will be exhibiting at productronica in Munich from November 14 – 17, 2023.
The topic of intrinsic copper structure has been largely neglected in discussions regarding the PCB fabrication quality control process. At face value, this seems especially strange considering that copper has been the primary conductor in all wiring boards and substrates since they were first invented. IPC and other standards almost exclusively address copper thickness with some mild attention being paid to surface structure for signal loss-mitigation/coarse properties.
At PCB West, I sat down for an interview with John Andresakis, the director of business development for Quantic Ohmega. I asked John to update us on the company’s newest materials, trends in advanced materials, and the integration of Ticer Technologies, which Quantic acquired in 2021. As John explains, much of the excitement in materials focuses on laminates with lower and lower dielectric constants.
Printed circuit board (PCB) reliability testing is generally performed by exposing the board to various mechanical, electrical, and/or thermal stimuli delineated by IPC standards, and then evaluating any resulting failure modes. Thermal shock testing is one type of reliability test that involves repeatedly exposing the PCB test board to a 288°C pot of molten solder for a specific time (typically 10 seconds) and measuring the number of cycles it takes for a board’s copper layer to separate from the organic dielectric layer. If there is no delamination, fabricators can rest assured that the board will perform within expected temperature tolerances in the real world.