Strain Gage Testing: Standardization

Estimated reading time: 10 minutes

As the electronics industry shifts toward finer-pitch BGA components, thinner PCBs and lead-free interconnects, the robustness of second-level interconnects (SLIs) may be affected adversely. This has led to concerns of SLI failure due to excessive flexure. Board-flexure control using strain gage measurement has become an effective method for preventing these failures.

By Mudasir Ahmad, Rich Duggan, Tom Hu, Brett Ong, Carter Ralph, Sundar Sethuraman and Dongkai Shangguan

Concerns about second-level interconnect (SLI) failures due to excessive flexure during board- and system-level assembly and test operations increase with the use of finer-pitch BGA components, thinner PCBs and lead-free interconnects (Figure 1). Of particular concern are brittle fractures on BGA components with an Electroless Nickel/Immersion Gold (ENIG) finish.1 Excessive flexure can sever the SLI and traces, resulting in reduced product yield for the manufacturer. Partial cracking, however, is not detected easily with non-destructive testing, and often appears only in field returns. Board-flexure control using strain gage measurement has proven effective in preventing these occurrences, and continues to gain acceptance as a method to identify stressful processes during manufacturing, handling, testing and assembly.

Figure 1. Second-level interconnect (SLI).

Strain gage testing (SGT) allows objective analyses of strain conditions that SMT components are subjected to during assembly and test. The process involves attaching strain gages on circuit board assemblies at specified locations (Figure 2). Dynamic strain measurements are captured for all manufacturing and test processes. Process steps with excessive strain are identified for optimization.

Figure 2. Strain gage instrumented test board.

With SGT, board assemblers can expect increased production yields. ‘Unavoidable’ failures, such as BGA fracture, historically attributed to bad components, now can be traced to specific manufacturing sequences or design features, and subsequently eliminated. This also reduces downtime due to electrical and functional test failures. Test-fixture vendors also can use SGT to validate their products, component suppliers to characterize component-package robustness and system designers to optimize enclosure and board support/stiffener designs.

Over the last year, a working group of computer systems companies, device/component vendors, EMS providers and strain gage equipment suppliers has been developing industry guidelines for SGT on PCBs. The team’s goal was to work toward the standardization of SGT and to drive its adoption as a common characterization process in the industry. The first step in this direction will be the upcoming release of the IPC/JEDEC-9704 Printed Wiring Board Strain Gage Test Guidelines.

IPC/JEDEC-9704

With increased utilization of strain measurement in electronics manufacturing, different SGT methodologies have been developed. Unfortunately, variations in methodology inhibit reliable data collection and prevent data comparison. IPC/JEDEC-9704 provides comprehensive SGT guidelines, which include gage mounting, gage placement, equipment calibration, experiment design, data acquisition system variables and strain metrics. This information will enable companies to execute SGT in a standardized and consistent manner.

The document also provides reference strain limits. In practice, customer or component suppliers typically define strain limits. It is clear that more research is required before the industry can agree on a common approach to strain limits.

The development of such limits has been facilitated by the publication of IPC/JEDEC-9702, Monotonic Bend Characterization of Board-Level Interconnects. Where IPC/JEDEC-9704 focuses on manufacturing assembly and test characterization, IPC/JEDEC-9702 seeks to develop a common approach to determining acceptable strain limits by component suppliers.

Manufacturing Process Characterization

For EMS providers, SGT serves as a process-characterization tool and allows the pro-active identification of high-strain sequences during assembly and test. In addition to isolating potentially problematic operations, SGT validates that processes are operating within allowable strain levels. This information is critical for EMS providers and their customers as it provides assurance of a safe assembly process. This is why many manufacturers are required to operate under strain levels specified by their customers or component suppliers.

Manufacturers also have been aggressively developing SGT capability and consistent processes for use across their factories. In moving toward standardization of test processes across global manufacturing sites, EMS providers have begun to adopt IPC/JEDEC-9704 as a framework for implementation, and have deployed standardized equipment, software and calibration tools across global manufacturing sites.

This standardization effort has allowed the creation of a central database of SGT results with the long-term goal of developing better test fixture, PCB layout and process setup methods and guidelines. With the insight that this data provides, companies are better positioned to design and manufacture more mechanically reliable products.

Component Strength Characterization

Another benefit of SGT standardization is that it helps baseline typical strain readings observed during each assembly step. Such baseline data can give component suppliers better estimates of end-use strain levels applied to devices. These estimates will, in turn, help suppliers define the strain targets necessary for their devices. EMS companies then can include the strain response of packages as a factor in the component-selection process.

Strain-related metrics provide component suppliers with a significant competitive advantage. Such strength-based comparative evaluation was not conceivable before the standardized implementation of SGT.

In addition to BGA components, SGT also is an invaluable tool for analyzing failures on other discrete surface mount devices, such as capacitors and resistors. These devices, though less susceptible than BGAs, can develop cracks that could propagate in field operations. Some capacitor vendors specify allowable strain limits.

Test-fixture Validation

The high strain imposed by clamps and test probes often make test fixtures a major culprit of solder-joint fracture due to excessive board flexure. While strain measurement of ICT fixtures is a critical application of SGT, adoption by test-fixture vendors is limited. Few leading fixture suppliers have embraced SGT as part of their product-validation process. Most rely on customers to conduct these tests (Figure 3).

Figure 3. ICT fixture validation.

For many vendors, cost is an important factor when implementing routine SGT on their fixtures. However, it is important to note that pro-active SGT can result ultimately in significant cost savings. The upfront use of SGT will help discover, isolate and correct high-strain/strain-rate events inherent to the fixture. This reduces “line-down” situations that may occur due to strain-induced component failures.

As awareness increases, it becomes obvious that SGT is a necessary tool for test-fixture vendors. It is hoped that this will spark a paradigm shift in the way ICT-fixture suppliers validate products.

Strain Gage Test Equipment

With the recognition that a growing need exists for the SGT of PCBAs, manufacturers of strain gages and related instruments have been developing products (including applications know-how) to meet the needs of users in this industry. Instrumentation/data acquisition equipment and software are being developed to address the needs of this market.

Perhaps the most pressing area of development is that of real estate, particularly in mobile computing platforms and small consumer devices. Circuit board designs are becoming increasingly small and dense; the available space to attach strain gages, solder wires to the tabs of the strain gages and to route wires/cables has been reduced greatly.

In more spacious designs, tooling holes and other obstructions may be present where a gage should be placed. Removing components can alter the mechanical response of the board, repositioning gages can result in irrelevant strain. Smaller gage sizes can be more susceptible to variations in the board structure and localized strain concentration. This lack of space and the increasing need for speed (to minimize sample preparation and test time), has led strain gage manufacturers to develop small planar and stacked rosette strain gages with thin, pre-attached wires/cables that cater to circuit board SGT specifically (Figure 4).

Figure 4. Stacked rosette strain gage with pre-attached wires.

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System Design

There also is a growing realization that fractures do not occur strictly on the manufacturing line. The diversity of applications for electronic devices has led to increased severity of shock loading, as well as a larger range of shock impulses that are applied based on the usage environment. This ranges from multiple high-acceleration shocks experienced by handheld devices to shipping-shock impulses on expensive enterprise infrastructure equipment.

Aside from manufacturing characterization, SGT also can be used as a mechanical design-validation tool. When paired with computational analysis techniques, SGT provides insights on the stresses that critical packages are subjected to during such conditions. This facilitates the development of more effective enclosure and stiffer designs. This data also can aid board designers when placing critical packages.

An effort sponsored by the IPC-610-D (SMT Attachment Reliability Test Methods) Committee seeks to develop a standardized shock test method, IPC-9703 Shock Test Development Methodology and Testing Techniques. This standard addresses the development and application for shock testing to surface mount components on PCBs. The document sets forth methodologies for determining the usage environment at the system level - designing representative board and component-level tests that can be used to judge robustness for the application.

There is a critical need for this test method, as designing test conditions that can replicate these varied environments is becoming increasingly difficult. To further complicate matters, a single component may be subjected to many distinct system environments, leading to confusion about component qualification testing.

Lead-free Transition

As we approach the July 2006 lead-free deadline, the transition to lead-free processes continues to cause anxiety. Of particular concern is the impact of lead-free solder on the reliability of PCBA interconnects. This is critical during the early stages of the transition, a time when the industry has limited data on the effects of new elements introduced in the PCB, components and solder joints.

While BGA package and overall system-design trends have decreased flexure tolerances, the switch to lead-free solder alloys has introduced fresh concerns. The primary issue is the increased stiffness of the lead-free solder alloys, which prevents the outer rows of solder balls from distributing as much stress to adjacent rows. Even though the strength of the solder joints has not changed significantly, the change in mechanical properties concentrates the stresses on outer solder balls, causing them to reach critical loads more quickly. Preliminary tests conducted by a component supplier have shown that this change can decrease the flexure tolerance of BGA packages by up to 40%. Many manufacturers may find flexure to be a problem as they ramp up to full lead-free production.

Lead-free Sn/Ag/Cu (SAC) solder alloy has a higher modulus, and its mechanical performance is known to be more sensitive to the strain rate, as compared to eutectic Sn/Pb solder. Research has shown that SAC experiences a higher degree of strain hardening than the Sn/Pb solder. The reliability comparison between SAC and Sn/Pb under bending is not yet clear. Research is still on-going to assess whether SAC may be more fragile due to the formation of the interfacial intermetallics and the associated existence of Kirkendall voids near the interface.

Furthermore, as the modulus of SAC is higher, it transmits more loading to the PCB and components. Data are being accumulated by the industry on the reliability of components that are subjected to the higher soldering temperatures for SAC. Higher soldering temperatures also can have an adverse impact on the reliability of the PCB, inducing failure modes such as warpage, delamination and Cu-trace cracking.

In the interim, as the lead-free transition is made for high-end products, the presence of mixed solder systems (such as lead-free solder balls with tin/lead paste) poses further questions on the impact of strain/strain rates on these mixed-solder metallurgies.

These concerns demand that the bending and flexure of the PCB during assembly, test, handling and transportation, as well as actual product application, be characterized and controlled closely to safeguard the reliability of the lead-free PCBA interconnection. Because SGT is a key method for such characterization, the release of IPC/JEDEC-9704 may arm companies with the knowledge necessary as the industry faces this challenging transition.

Conclusion

As SGT continues to gain momentum in the electronics industry, it is clear that it has evolved from a simple failure-analysis method to a standardized process-characterization tool. However, before the industry can fully realize the benefits of SGT, there are more hurdles that should be overcome. There is the need for more collaborative research on the topic of strain limits. Efforts to reduce the cost of testing will ease adoption by smaller companies.

While the industry may never be able to fully eradicate solder-joint fractures, the use of SGT will help companies develop more robust manufacturing processes and increase product quality and reliability levels.

The authors thank members and participating companies of the IPC/JEDEC-9704 working group for contributing to the development of the SGT guidelines.

REFERENCES

1. “Strain Gage Testing: Predicting and Preventing Brittle Fracture of BGAs”, SMT, June 2004, Julia Goldstein, 87.D.

Mudasir Ahmad, manufacturing engineer, Cisco Systems, may be contacted at (408) 853-9201; mudasir.ahmad@cisco.com; Rich Duggan, director of engineering services, Circuit Check, may be contacted at (763) 694-4247; rich.duggan@circuitcheck.com; Tom Hu, manufacturing engineer, Intel, may be contacted at (480) 552-2656; tom.hu@intel.com; Brett Ong, manufacturing engineer, Sun Microsystems, may be contacted at (408) 907-9565; brett.ong@sun.com; Carter Ralph, packaging engineer, Intel, may be contacted at (480) 554-8306; carter.w.ralph@intel.com; Sundar Sethuraman, process engineer, Solectron, may be contacted at (408) 956-6545; sundarsethuraman@ca.slr.com; Dongkai Shangguan, Ph.D., director, advanced process technology, Flextronics, may be contacted at (408) 428-1336; dongkai.shangguan@flextronics.com.