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Fighting the War on FailureAugust 11, 2015 | Andy Shaughnessy, PCBDesign007
Estimated reading time: 3 minutes
In the August 2015 issue of The PCB Design Magazine, the focus is on the “War on Failure,” a war that your company is likely already prosecuting. The big question is this: Can we ever win this war?
No one in this industry sets out to fail, except failure analysis test engineers. But failure is a part of life for designers and manufacturers of electronics. Our reader surveys show that failure affects nearly everyone in the PCB industry: designers, fabricators, assembly providers, OEMs, and suppliers.
And failure itself is difficult to define; everyone has a different definition.
The meaning of “failure” seems to evolve over time. Think about this: The PCB design process of the past would be considered a failure today. Decades ago, many PCB designs went through multiple design iterations and board re-spins. No one labeled those actions as failures; it’s just the way the process worked back then.
There was no hand-wringing about it, no post-mortem meetings full of downcast faces, wondering what went wrong. That was the accepted practice. I bet design managers included these multiple steps in their department’s flow charts.
Multiple iterations and board re-spins weren’t an issue until price and time-to-market made them an issue. Once high-speed PCBs became the norm, doing redesigns and building prototype after prototype was no longer financially feasible. Design teams began using simulation and analysis, the “right the first time” movement took off, and now we look at the old way as a failure.
The same holds true for PCB fabrication and assembly providers. The scrap rates of the past would run a company out of business today. Now, manufacturers are adopting processes like Lean and Six Sigma to help eliminate as much waste as humanly possible. Six Sigma’s 99.997% rate of perfection is no longer considered an unattainable dream.
What Does Failure Mean to You?
That was one of the first questions I posed in our cover story interview, “Kelly Dack and Mark Thompson Unite in the War on Failure.” Kelly and Mark come from design and CAM backgrounds, respectively, and they’ve teamed up in this ongoing battle. In this interview, they discuss their definition of failure, some of the more common failures they see from their perspectives, and a variety of ways to keep failures to a minimum. But as they point out, we’ll probably never eliminate failure completely from the PCB industry.
Paul Reid’s feature column, “Failure Mode: Hole Wall Pullaway,” details how stress-relieving and stress-inducing HWPA can cause copper plating in a plated through-hole to be pulled away from the dielectric of the hole wall. As usual, Paul brought along a few of his super cool cross-section animations that show these defects as they happen.
In Tim Haag’s feature column, “Failure May Not be an Option, But Sometimes it’s a Reality,” he discusses some of the mistakes, miscues, and missteps that are common among PCB designers. Working off the famous line by Ed Harris’ character in Apollo 13, “Failure is not an option,” Tim explores everything from not using all of your EDA tool’s inherent capabilities to using far too much automation.
In “Mentor Graphics Helps Bridge Gap between PCB and RF,” Barry Matties interviews Per Viklund, director of IC packaging and RF product lines for Mentor, and Business Development Manager Alex Caravajal. Per and Alex explain how Mentor is helping bring together the RF and PCB design worlds, and their plans to accelerate the RF design cycle.
We also bring you the latest in columnist Barry Olney’s continuing series, “Stackup Planning, Part 3.” This month, Barry looks into stackup configurations for high layer-count, high-speed PCBs, with some stackup tricks for eight-layer designs.
Columnist John Coonrod offers a “Brief Overview of High-Frequency Laminates,” explaining their moisture absorption challenges, thermal properties, and thickness control. He also addresses the use of special fillers to achieve good CTE values and greater stability.
DfR Solutions’ Tom O’Connor offers an update on the ongoing shortage of engineers graduating in North America in “Training the Next-Generation Engineer: When Does it Begin and End?” Tom focuses on the efforts to attract more smart young students to the STEM disciplines, and the need to jump-start these efforts right now, before it’s too late.
I’ll see you next month, when we devote the September issue to automotive electronic design. Enjoy the last of your summer—show time is around the corner!
There has always been pressure to reduce line and space as we have seen the bleeding edge technology go from 8 mils to 5 mils and then to 3 mils. The difference between “then” and “now” is that the prior advancements, for the most part, used the same processes, chemistry and equipment going from 8 mils to 3 mils. But going from 3 mil to sub 1 mil trace and space is a quantum leap in printed circuit board (PCB) technology that requires a whole new set of processes and materials.
In a previous column, the critical process of desmear and its necessity to ensure a clean copper surface connection was presented. Now, my discussion will focus on obtaining a void-free and tightly adherent copper plating deposit on these surfaces. After the desmear process, the task is to insure a continuous, conductive, and void-free deposit on the via walls and capture pad. Today, there are several processes that can be utilized to render vias conductive.
Panasonic’s Darren Hitchcock spoke with the I-Connect007 Editorial Team on the complexities of moving toward ultra HDI manufacturing. As we learn in this conversation, the number of shifting constraints relative to traditional PCB fabrication is quite large and can sometimes conflict with each other.
MKS’ Atotech, a leading surface finishing brand of MKS Instruments, will participate in the upcoming IPCA Expo at Bangalore International Exhibition Centre (BIEC) and showcase its latest PCB manufacturing solutions from September 13 – 15.
Flexible circuit applications can be as basic as furnishing electrical interconnect between two conventional circuit board assemblies, or to prove a platform for placing and interconnecting electronic components. During the planning and pre-design phase of the flexible circuit, there will be several material and process related questions that need to be addressed. Most flexible circuit fabricators welcome the opportunity to discuss their customers’ flexible circuit objectives prior to beginning the actual design process.