Fresh PCB Concepts: Key Considerations for Reliability, Performance, and Compliance in PCBs
Elementary Mr. Watson: Navigating RF—A Glide Path Approach to Design Success
Designers Notebook: Layer Stackup Planning for RF Circuit Boards
Orange Co. DC Chapter Meeting: PCB Cost Adders
June 1, 2016 | IPC Designers Council, Orange Co. ChapterEstimated reading time: 1 minute
The Orange County Chapter of the IPC Designers Council will hold a "Lunch 'n' Learn" meeting on Wednesday, June 15 in Irvine, California. Guest speaker Julie Ellis of TTM Technologies will focus on PCB cost-driving factors that should be considered early in the design phase to save your company money.
A designer is faced with many challenges when planning your layout to achieve a balance of performance, quality and reliability versus cost. In this presentation, Julie Ellis of TTM Technologies will discuss the many factors that contribute to cost and explore the trade-off considerations for design optimization.
She will explore panel utilization, layer count, material selection, via structure choices, via-filling options, the impact of various sequential laminations, plating processes, surface finishes, scoring, milling and back drilling. Attendees will learn various rules of thumb to help you make better choices for mitigating the cost of the boards you design.
Reserve a spot on your calendar on Wednesday, June 15 from 11:30 am to 1:30 pm for this educational “Lunch ‘n Learn” meeting event.
Date: Wednesday June 15, 2016
Time: 11:30 am - 1:30 pm
Where: Harvard Athletic Park multi-purpose room, Irvine, California
Please RSVP no later than noon on Tuesday, June 14, 2016
There are two ways to RSVP:
- Click here to RSVP
- Or email your RSVP to terri_kleekamp@mentor.com.
Location
Harvard Athletic Park
14701 Harvard Ave.
Irvine, California 92606
(The multi-purpose room is at the SOUTH end of the athletic fields)
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