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Chuck Bauer Discusses the Future of Packaging
September 5, 2018 | I-Connect007 Editorial TeamEstimated reading time: 2 minutes
When we decided to cover the future of PCB packaging, we knew we would have to interview Charles Bauer, Ph.D., owner of TechLead Corporation. For over 35 years, Chuck has been a pioneer in electronics packaging, from 3D and system-in-package to multichip modules and nano technology. He’s a frequent speaker at events like SMTA International, ICEP Japan and ESTC in Europe. He also founded the Pan Pacific Microelectronics Symposium.
Chuck recently spoke with Happy Holden, Andy Shaughnessy and Barry Matties about current trends in packaging, the need for product designers and manufacturers to communicate, and why no matter how cool the technology is, cost is still king.
Happy Holden: Chuck, some of the big trends are 3D packaging and wafer-level packaging. Wafer-level packaging is of interest to a lot of our readers because the organic package substrate is a leading edge for circuit board technology. With this wafer-level packaging push, it wants to be finer and finer pitch. What does that do to the assembly, Chuck?
Bauer: First, I think that wafer-level packaging is really a misnomer because wafer-level packaging isn't really being done so much at the wafer level anymore. There's fan-in, wafer-level packaging, which is indeed a wafer-level packaging approach. That's relatively limited today, and I think that some of the barriers in terms of interfacing with circuit boards are going to inhibit that technology. It doesn't mean it can't be done or won’t be done; it just means it's going to be inhibited in terms of pin-count because their pitch is going to be constrained by the next level of interconnection.
There are countervailing trends in the assembly side of the industry, where we're seeing a lot more activity going on in the area of nano assembly. For example, about four years ago we did a project that had a wafer-to-wafer connection. We used a nano silver technology to join a CMOS pre-amplifier chip directly to an indium phosphide avalanche photo diode. We were connecting those two chips to each other, and we were doing it on a 32-micron pitch with 6-micron pillars. Today, they're down to about 22-micron pitch, and the goal is to get it to 15-micron pitch.
IBM Zurich has been very active in using nano copper as the bonding medium to assemble fine-pitch packages down to about 40-micron pitch onto printed circuit boards. I think that there will necessarily be materials development that will allow us to achieve those finer pitches. How fine a pitch we have to go to is a different question. As we go to too fine a pitch, what happens to the printed circuit board? I do think that, especially in the kinds of products that are going to use these super fine pitch devices, you're starting to see a trend toward more and more flex and flex rigid type structures.
The one area where those packages are going to be a big player is in areas such as IoT. No other markets are big enough to justify processing of devices at a panel level like that, because most of the technologies that we use, and most of the designs that we use, just don't use enough volume to justify putting together a panel processing line, when you look at the capacity.
To read this entire interview, which appeared in the August 2018 issue of Design007 Magazine, click here.
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