IPC High-reliability Forum and Microvia Summit Review, Part I

Estimated reading time: 6 minutes

The IPC High-Reliability Forum and Microvia Summit—held in Hanover, Maryland, May 14–16, 2019—focused on IPC A-610 Class 3 high-reliability electronics for critical military, aerospace, automotive, and medical applications required to function without interruption for an extended lifetime where downtime was not acceptable. The event covered a broad range of topics related to reliability and provided interactive opportunities to share expert knowledge and experience in determining and understanding the causes of failure and selecting the best design rules, materials, processes, and test methods to maximise product reliability.

John Bauer, STC program manager with Collins Aerospace, was the keynote speaker. The theme of his presentation was designing for reliability: “You’re only as strong as the weakest link.” And in this context, via holes constituted the “weakest link.”

Referring to the myriad of electronic systems and devices used in commercial aircraft, Bauer commented that products were expected to last upwards of 20 years in the field, enduring operational temperature extremes between -40 and +85°C. He reviewed the accelerated thermal cycling and thermal shock test methods used as indicators for field reliability and described in detail the qualification testing of via interconnects by monitoring change in resistance. By disciplined supply chain management—especially the use of qualified materials and the meticulous selection of PCB vendors with defined technology capability combined with accredited quality systems and reliability testing procedures—the incidence of confirmed microvia defects had been reduced to zero in 2017 and 2018 for a total of over a billion microvias purchased over those two years.

Next, Bauer showed many real examples of microvia failure. His list of root causes included aspect ratio greater than 1:1, debris entrapment from secondary machining operations, inadequate cleaning, unauthorised process changes, overheating of target pads during laser drilling, inadequate throwing power of copper plating, and poor supplier selection.

So, what were the attributes of reliable microvias? Bauer recommended aspect ratios of less than 0.75:1, ablated diameters greater than 0.005”, target pad diameters greater than 0.012”, and two-ply construction with spread-glass prepreg. He recommended choosing the most reliable from this list to suit the particular end-use application: open-plated microvias, full-plated single layer microvias, staggered microvias, two-stacked microvias, and three-stacked microvias (based on his experience and in descending order of reliability).

Bauer then showed test results demonstrating the comparative reliability of different via structures from qualified PCB suppliers followed by examples of stacked microvia and microvia-on-buried-via structures that had failed qualification. Variables that significantly affected reliability were via-fill material selection, tin-lead versus lead-free reflow, and the diameter and aspect ratio of buried vias.

Yaad Eliya, CTO of PCB Technologies in Israel, also reviewed new applications and innovative solutions for RF microwave. In his presentation, he discussed the benefits of incorporating air-cavity and air-tunnel technologies in PCB designs for radar systems operating at GHz frequencies. Instead of designing multiple systems each with a discrete frequency, these technologies enabled a significant increase in bandwidth such that a single module could cover multiple radar signatures as well as saving weight and cost.

Eliya went on to compare the attributes of standard materials, such as low-Dk FR-4 laminates, proprietary woven glass-reinforced hydrocarbon-ceramic laminates, and flexible polyimide laminates with enhanced materials—including PTFE-ceramic laminates, proprietary “very low-loss” laminates, fluoropolymer-polyimide composite flexible laminates, and glass-microfibre-reinforced PTFE composites. He also discussed the effects of raw materials, fillers, glass styles, and copper foil surface roughness on high-frequency performance and signal integrity before offering practical guidance on design rules for soft materials and embedded-component procedures. Eliya then gave general guidelines for selecting heat dissipation solutions and recommended using highly accelerated thermal stress testing for material and process optimisation.

Terry Munson, founder and president of Foresite Inc., explained that a conductive anodic filament (CAF) failure was an electrical short occurring inside the PCB as a result of a conductive filament forming in the laminate dielectric material between two adjacent conductors under a DC electrical bias and humidity. His presentation demonstrated that resin starvation in the glass weave at a via location could allow plating chemistry to penetrate the weave and create the conditions for an inner layer CAF short under normal operating power. The principal structural difference between CAF and dendrite growth was that the former was internal and the latter external.

External dendrite shorting could result from no-clean flux residue incompletely heat-activated, water-soluble flux not properly cleaned, condensing water between conductors, contamination from outside sources, or fabrication residues on the PCB and components. Munson set out to find answers to the logical questions. Do these contaminants and moisture pass into the PCB inner layer and cause the same issue? How do moisture and corrosive contaminants get into the weave of the board? Wouldn’t the outside create shorts on top of the mask or under the mask first? If the corrosive residue cane in though the via, wouldn’t there be signs of the copper barrel corroding?

Using a series of case-history examples illustrated by a combination of optical microscopy and X-ray with scanning electron microscopy and energy-dispersive spectroscopy, Munson demonstrated the effects of resin starvation in the laminate, rough drilling of via holes, and surface contamination from etch and rinsing processes during inner layer fabrication on the formation of CAF shorts. Furthermore, he believed that CAF failures resulting from fabricator process control issues might only show up on a specific panel in a stack of pressed panels.

Dr. Mike Bixenman, VP and CTO of Magnalytix—a joint venture between KYZEN Corporation and STI Electronics—was an advocate of surface insulation resistance (SIR) testing as a means of gathering real-time objective evidence of cleanliness for determining the reliability of electronic assemblies and mitigating the risk of failure. Cleanliness was a key reliability factor as functionality increased, designs became denser, component packaging clearances became smaller, and operating environments became harsher.

How could ionic cleanliness be meaningfully measured? The industry had for many years relied upon resistivity of solvent extract (ROSE) testing, but it has now been recognised that this method is obsolete and is no longer considered an acceptable basis for qualifying a manufacturing process. Amendment 1 to IPC J-STD-001G was a major revision of the J-STD-001 cleanliness requirements and changed how the industry would address future cleaning and residue requirements. For high-reliability assemblies, soldering and cleaning processes would be qualified in terms of acceptable levels of flux and other residues as determined just prior to application of conformal coating. “Acceptable” and “unacceptable” levels of residues on production hardware would be determined, and the risks associated with contamination identified, analysed, controlled, and monitored to eliminate risks or mitigate their effects.

Bixenman also discussed humidity-related failure modes where trapped residues left from soldering and handling could result in dendritic growth, conductive anodic filament formation, electrochemical migration, migration under conformal coating, and gas corrosion, especially under harsh climatic conditions. He described the principal elements of an effective SIR test system designed for use at the production floor. These included a certified high impedance meter and power supply, matrix switching cards for eight test board slots (each with four channels per board), highly shielded cables for very low noise and crosstalk when measuring high SIR values, a real-time user interface run live during testing with high processing speed, outputs for analytics and data, and facilities for SPC and internet-enabled report generation with the ability to fully control the environmental chamber.

The SIR test method was effective at testing for residue effects, incoming bare board cleanliness, material investigations and qualifications, and the prediction of long-term failure mechanisms. The system Bixenman described could be used for on-site process characterisation, process development, and process optimisation, and he showed many application examples in PCB system design, process development, process control, and product acceptance.

Watch this space for Part II of this review.