-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLevel Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
Opportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
Best Practices: Footprint Design and CAD Library Management
February 9, 2021 | I-Connect007 Editorial TeamEstimated reading time: 2 minutes
The I-Connect team spoke with Altium’s John Watson about the hurdles surrounding footprints and footprint design. John talks about how being proactive and improving the CAD library can better QC processes and help protect against footprint difficulties.
Andy Shaughnessy: I’m here today with John Watson from Altium to discuss footprints, footprint design, and what can be done to achieve best practices. This came about because we recently conducted surveys asking for design problems. The results came mainly from designers, and around a quarter of them said footprint issues were a big problem.
John Watson: There’s a real conflict in a lot of companies. They want to get their product to market. So, I think that the first issue that comes in with anything in a design is this conflict between the management schedule and the design schedule. If you’re creating a new component, for example, number one is that component needs to be put into quarantine. It’s not used in new designs. It needs to be put into quarantine and checked. There’s such a rush to say, “We’ve got to get this done and get it out.” And there’s just too much going on in a design to catch things that are wrong like that.
Barry Matties: How long should it be in quarantine?
Watson: It stays in quarantine until a couple of processes are completed. Number one, there is a QC process that’s done on that component, and that QC process is actually multi-level. There will be different steps involved. For example, if you have a new component, you bring that component in or that footprint in, and you verify that footprint to the datasheet. On this first level of QC, you want to set up your verification documents to that footprint. What are we going to be looking at? We’re going to be comparing this footprint to the datasheet, we’re going to be looking at IPC standards, whatever the standards are that you’re going to be lining this footprint up with. That’s going to be your first level of QC, but I’ve actually seen where there’s a second level of QC that’s done. Once that part has been verified to the datasheet, that part then goes into what’s called the prototype status; what it does is that component is then put onto a PCB, kind of a live test.
When that board comes back with the component on it, you look at it under the scope to see if there are any issues with the soldering. It’s like a real-world environment. Those are the two levels of QC. Number one, you compare it to the documentation, and then you have a real-world environment that you take it through. That step and those processes are what you go through. That way, you’ve actually had both sides of it: You have your side of it, and then also the assembler’s side of it. I’ve found that a lot of times, believe it or not—I know it’s a shocking comment I’m about to make—but datasheets have been known to be wrong. VPs have no understanding of what it takes to put a PCB design out—the steps, the checks that you have to do, all these different things. Often, that’s lost in this whole process.
To read this entire conversation, which appeared in the February 2021 issue of Design007 Magazine, click here.
Suggested Items
Real Time with… IPC APEX EXPO 2024: My Role as a Technology Solutions Director
05/02/2024 | Real Time with...IPC APEX EXPOPeter Tranitz, senior director of technology solutions at IPC, shares insights into his role as the design initiative lead. He details his advocacy work, industry support, and the responsibilities of the design initiative committee. The conversation also covers the revamping of standards, the IPC Design Competition, and the implementation of design rules in software tools.
Real Time with… IPC APEX EXPO 2024: Ventec Discusses New Pro-bond Family of Advanced Products
05/01/2024 | Real Time with...IPC APEX EXPOChris Hanson, Ventec's Global Head of IMS Technology, outlines the launch of four pro-bond formulas that deliver an outstanding combination of low dissipation factor (Df) with a dielectric constant (Dk) range to maximize the design window for critical PCB parameters. As Chris points out, Pro-bond is designed for low-loss, high-speed applications, while thermal-bond dissipates heat from a component through the board to a heat sink.
IPC's Vision for Empowering PCB Design Engineers
04/30/2024 | Robert Erickson, IPCAs architects of innovation, printed circuit board designers are tasked with translating increasingly complex concepts into tangible designs that power our modern world. IPC provides the necessary community, standards framework, and education to prepare these pioneers as they explore the boundaries of what’s possible, equipping engineers with the knowledge, skills, and resources required to thrive in an increasingly dynamic field.
On the Line With… Talks With Cadence Expert on SI/PI for PCB Designers
05/02/2024 | I-Connect007In “PCB 3.0: A New Design Methodology—SI/PI for PCB Designers,” subject matter expert Brad Griffin, Cadence Design Systems, discusses how an intelligent system design methodology can move some signal and power integrity decision-making into the physical design space, offering real-time feedback.
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.