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Does Copper Pour on a Signal Layer Decrease Signal-To-Signal Isolation?
April 7, 2022 | Steve Hageman, Analog HomeEstimated reading time: 1 minute

Does putting a ground pour on PCB signal layers make the isolation better or worse? It can go either way, but with the proper knowledge and application, this technique will improve your designs.
In this article, I’ll discuss how to simulate trace-to-trace isolation with true electromagnetic simulation software. We’ll also cover a variety of rules of thumb that can help you stay away from trouble.
Fact or Fiction?
Recently an acquaintance told me, “I have heard that putting a copper pour on a signal layer between traces actually makes the isolation between the traces worse.” I grabbed one of my RF boards and said, “If that is so, then how do all these RF boards that I have done with co-planar waveguide over ground manage to function? They all have copper pours on the signal layer, and they work to very high frequencies.”
Since co-planar waveguide over ground (CPWG), which is essentially “pouring copper on a signal layer,” is used for a lot of RF work, and is proven to work for very high-performance RF circuits, how did this contradictory opinion catch on in the industry?
To investigate this, I used a one-inch section of 50-ohm microstrip consisting of an aggressor trace from ports 1 to 2 and a victim trace running in parallel from ports 3 to 4. I used typical values for the dimensions as might be on a real PCB. The trace width is 20 mils, with a spacing of 60 mils from center to center, over an FR-4 substrate, 9.5 mils thick, with a modeled Er of 4.4.
To read this entire article, which appeared in the March 2022 issue of Design007 Magazine, click here.
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Multicircuits Expands Capabilities with State-of-the-Art Automated Copper Via Fill Process
03/10/2025 | MulticircuitsMike Thiel, president of Multicircuits, a leading provider of high-reliability printed circuit boards, has announced the addition of a state-of-the-art automated copper via fill process to their advanced manufacturing capabilities. This strategic investment enhances the company’s ability to deliver cutting-edge solutions for demanding industries, including aerospace, defense, medical, and high-speed telecommunications.
EIPC 2025 Winter Conference, Day 2: A Roadmap to Material Selection
02/20/2025 | Pete Starkey, I-Connect007The EIPC 2025 Winter Conference, Feb. 4-5, in Luxembourg City, featured keynotes and two days of conference proceedings. The keynote session and first-day conference proceedings are reported separately. Here is my review of the second day’s conference proceedings. Delegates dutifully assembled bright and early, well-rested and eager to participate in the second day’s proceedings of the EIPC Winter Conference in Luxembourg.
Designers Notebook: Addressing Future Challenges for Designers
02/06/2025 | Vern Solberg -- Column: Designer's NotebookThe printed circuit board is and will probably continue to be the base platform for most electronics. With the proliferation of new generations of high I/O, fine-pitch surface mount semiconductor package variations, circuit interconnect is an insignificant factor. Circuit board designers continually face challenges such as component quantity and complexity, limited surface area, and meeting the circuit board’s cost target. The printed circuit design engineer’s prominent position demands the development of efficiently manufacturable products that perform without compromise.
DesignCon 2025, Day 2: It’s All About AI
01/30/2025 | Marcy LaRont, I-Connect007It’s hard to get away from the topic of artificial intelligence, but why would you? It’s everywhere and in everything, and my time attending presentations about AI at DesignCon 2025 was well worth it. The conference’s agenda featured engaging presentations and discussions focused on the technological advancements in AI, big data centers, and memory innovations, emphasizing the critical relationship between processors and circuit boards.