Real Time with... IPC APEX EXPO: Silicon Geometry's Signal Integrity Impact on PCBs

Estimated reading time: 5 minutes

At IPC APEX EXPO 2025, Kris Moyer addressed the importance of understanding the impact of silicon geometry reduction on signal integrity and PCB performance. As technology evolves, traditional design principles are increasingly challenged, requiring designers to adapt to new realities where even simple circuits must consider factors typically associated with RF applications. Kris says signal integrity considerations are necessary for so many designs today, regardless of clock frequency. He discusses valuable insights from attendees regarding embedded resistor technology and the effects of radiation on smaller silicon features in aerospace applications.

Marcy LaRont: This is Marcy LaRont with I-Connect007 and Real Time with… IPC APEX EXPO, and I'm here with Kris Moyer on the first day of the Professional Development sessions. Kris, you were one of the kickoff sessions this morning and your session was called “The Impact of Silicon Geometry Reduction on Signal Integrity and PCB Performance.” That was a lot in one sentence. Why was this an important session to include in the professional development this year?

Kris Moyer: Thank you, Marcy, for asking the question. This was an important session because, as the name implies, to do the board designs correctly nowadays, we have to understand what the silicon people, the NVIDIAs, the Qualcomms, the Intels and so on, what the impact of what they're doing in their chips and how it affects our boards.

We're seeing some impacts our industry has never seen before, and so I wanted to bring that information to the broader audience, the broader designers, so that they would understand and can make intelligent decisions when they're working on their designs.

LaRont: Well, you outlined many things that are not quite the same as they have been. Until very recently, in terms of the technological arc that we're on and how that affects those that design the products that we're creating or trying to create, you talked a little bit about Moore's Law and where we stand with that today. It’s a big topic of discussion you hear a lot. What are some of those things that you outlined?

Moyer: A couple of the key topics I brought up were the fact that, because of these changes in the silicon geometry, we see a need to apply signal integrity design principles to many, many product designs that never needed them in the past where we could say, you know, my traces are short enough. I'm not going to have any problems, et cetera.

Because of these silicon geometry changes at the IC level, we now have products that were never an issue before suddenly becoming an issue in markets that never would have considered them before. This is one of the big areas. So, the speed of the signals, the speed of the rising and falling edges, the fact that many of these designs now are starting to behave closer to RF geometries, which used to be a very niche market, and now we're seeing that spread more and more into standard designs, not just in the RF sections like the antennas and the Bluetooth and so on, but in the everyday simple circuits are. Now, we're having to start thinking of them like the RF engineers have had to think for many, many years.

LaRont: You pose the question, “At what point do I have to add signal integrity design considerations into my project?” And it feels more and more like the lines are blurred. I'm sure it's application dependent to some degree, but it's like almost always.

Moyer: Nowadays, it pretty much is almost always. As I pointed out in the class, one of the big misconceptions in the industry is that it's based off of clock frequency.

I've had discussions with many an engineer who says, “Well, I'm not running a fast clock. I'm running a very slow clock. I don't have a problem.” As I pointed out in the professional development courses, It's not the clock frequency because of the reduction in the silicon geometry size; it's that edge rate.

It's that rise time and fall time, which are really the deciding factors and those are solely dependent on the geometry of the silicon, which is one of the key features I pointed out in the course.

LaRont: Did you have any interesting questions come from the attendees?

Moyer: Yes, I had one very interesting question that came up. It was about the fact that when we have to start applying signal integrity, it means series termination resistors, and the fact is that we can no longer put necessarily physical series termination resistors. It’s because the distances that the termination resistor has to be from the pin are too small now for a physical resistor to be soldered onto the board. So I brought up the point of the embedded resistor technology.

And the question came up, “Should they use the screen printed embedded resistor technology or the action informed embedded research technology? And what are the reliability concerns?” These came up from several folks in the military and aerospace application. Another great question that came up is from a radiation hardening of these advanced silicon features: “As they get smaller and smaller, are they more susceptible to radiation issues?”

Again, this came from MilAero, specifically the aerospace side, satellites, and communications as they go to outer space and see these kind of radiation fields. How will the smaller and smaller silicon geometry be affected by those radiation fields and how can they mitigate those?

LaRont: I'm sure you have people who will follow up with you afterwards.

Moyer: Yes, I actually already had interest in a few of my additional design classes. My design for military and aerospace class and my design for advanced design concepts class, where I go over the embedded resistors and the shrinking geometries of the board features and so on.

LaRont: Kris, if you had to boil it down, what do you most hope attendees would take away from your session this morning?

Moyer: Number one. I hope that they have a better grasp and understanding of the interplay between the silicon design world and the board design world as well as having a better feel for and information they can use on their own jobs to help them do and create more efficient designs, more efficient, reliable designs for these signal integrity and high-speed digital designs and so on. Also, how that's going to help them be successful in their jobs and their careers.

LaRont: Well, that's great. Kris, thank you so much for talking with me. This has been with Kris Moyer, IPC instructor, and as we like to call him, the design guru. Thanks so much for tuning in.