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Symposium Review: A Glimpse Into the Future of IC Substrates and Beyond
January 27, 2026 | Edy Yu, Editor-in-Chief, ECIOEstimated reading time: 3 minutes
Editor’s note: Edy Yu, Electronic Chief Intelligence Officer (ECIO), is an I-Connect007 content partner in China. This article was originally featured in the Q4 2025 HKPCA Journal. Inquiries should be directed to edy@e-cio.cn.
The Hong Kong Printed Circuit Association (HKPCA) and the Korea Printed Circuit Association (KPCA), with strong support from SEMI, presented “The Future of IC Substrates and Beyond Symposium 2025” at the Sands Expo and Convention Centre in Singapore in . The event brought together elite professionals, technical experts, and corporate leaders from across the global IC substrate industry chain to explore cutting-edge trends and innovative solutions shaping the future of the sector.
The core topics of the symposium included innovations in glass substrate technology, co-design for heterogeneous integration, warpage control in large-size packaging, packaging technologies for AI and HPC applications, and emerging trends in SiC power semiconductor packaging. Together, these discussions provided a comprehensive overview of the developmental direction of the advanced packaging industry chain. Below is a brief recap of the symposium’s highlights.
Dr. Kelvin Pun, Goertek Microelectronics
Dr. Kelvin Pun, vice president of Goertek Microelectronics, delivered the first keynote, “Latest Advancement in Glass Substrate Technology for Advanced Packaging.” He emphasized that glass substrates, with their exceptional dimensional stability and smooth surface, offer outstanding performance in signal integrity and thermal management. As such, they are poised to become a key material for overcoming the limitations of traditional organic substrates.
Prof. Gu-Sung Kim, Kangnam University
Gu-Sung Kim, a professor at Kangnam University, discussed “Co-Design Considerations of Heterogeneous Integrated Package and Substrate,” emphasizing the importance of system-level co-optimization. With the growing adoption of chiplet architectures, the boundaries between packaging and system design are becoming increasingly blurred, underscoring the urgent need for new design automation tools.
Allen Cheah, AT&S
Allen Cheah of AT&S presented “Meeting AI Challenge-Large Package Solution and Warpage Management for Advance Substrates.” He provided a detailed analysis of the warpage and deformation issues that occur during the manufacturing of high-power-density circuits and packages, and showcased the latest research progress in multilayer structural optimization and stress control. He also mentioned that by 2030, global semiconductor industry revenue is expected to reach $1 trillion, and advanced integration packaging technologies such as 2.5D and 3D will play a pivotal role in meeting the performance demands of AI clusters and high-performance computing systems.
Youngseob Shin, Amkor Technology
Youngseob Shin of Amkor Technology delivered a comprehensive review on “AI/HPC Advanced Substrate Technology Overview,” noting that modified semi-additive process (mSAP) and hybrid substrate structures are expected to become mainstream.
Ben Kim, Onsemi Korea
In the afternoon session, Ben Kim from Onsemi Korea presented on “Silicon Power Semiconductors and Packaging Technology,” emphasizing the superior performance of SiC materials under high-voltage and high-temperature conditions, which make them a crucial foundation for the electric vehicle and new energy industries.
Rambo Sun, Bomin Electronics
Rambo Sun, Chief Technology Officer at Bomin Electronics, shared insights on “Development and Characteristics of Advanced Packaging Substrate.” His presentation focused on the company’s research and achievements in the IC substrate field, covering technological advancements in substrate materials and their integration with semiconductor components. Innovations in glass and organic substrates were highlighted as key to achieving higher reliability, signal integrity, and mechanical stability. Future developments in packaging substrates, he noted, will emphasize improving material properties—such as reducing the coefficient of thermal expansion (CTE), enhancing signal integrity and mechanical strength.
Chiwon Hwang, Samsung Electro-Mechanics
Finally, Dr. Chiwon Hwang of Samsung Electro-Mechanics concluded the session with “Substrate Technology and Trend for High-Performance Semiconductor Packages.” His presentation provided a comprehensive overview of advanced packaging technology developments and trends, covering multiple aspects including the evolution of packaging, power and thermal management, materials and design challenges, signal integrity and noise reduction, and progress in substrate technologies.
A dynamic panel discussion reached three main points of consensus:
- Cross-disciplinary collaboration among materials, design, and manufacturing will determine future competitiveness
- AI-driven design optimization and simulation will become a new engine for packaging development
- Green manufacturing and sustainable materials will become a crucial direction in the transformation of the industry value chain
This symposium not only showcased the latest scientific and technological achievements, but also established an international platform for communication and collaboration, further advancing the frontiers of electronic manufacturing and advanced packaging technologies.
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Rachael Temple - AlltematedSuggested Items
MacDermid Alpha to Address Silver Price Volatility Solutions at ECTC 2026
05/15/2026 | MacDermid AlphaAs volatile silver prices continue to place pressure on semiconductor packaging costs and supply chain predictability, MacDermid Alpha Electronics Solutions will highlight material strategies that help manufacturers reduce dependence on silver without sacrificing reliability, thermal performance, or manufacturing efficiency.
What Heterogeneous Integration Means for EMS Providers
05/14/2026 | Nolan Johnson, I-Connect007Dr. Ravi Mahajan, an Intel Fellow and Director of Intel’s Technology and Pathfinding group, delivered a keynote at the APEX EXPO 2026 technical conference on using heterogeneous integration (HI) as a strategy and on how advanced packaging technology serves as the technical apex for implementing that strategy. Mahajan’s previous papers and industry presentations on such topics as interconnect density, signal integrity, power delivery, thermal path, and assembly yield as system-level constraints confirm him as an expert on package optimization.
System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor
05/14/2026 | Chetan Arvind Patil, Marvell TechnologyIn conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.
I-Connect007 Announces Upcoming Issue of Advanced Electronics Packaging Digest
05/13/2026 | I-Connect007The next issue of Advanced Electronics Packaging Digest examines the materials, architectures, and integration strategies shaping the next phase of electronics innovation, from reinforcement materials under thermal and frequency pressure to heterogeneous integration and advanced packaging as a system-level scaling factor.
ASE, WUS Announce Strategic Collaboration to Build Advanced AI Packaging Hub in Kaohsiung
05/08/2026 | ASE GroupAdvanced Semiconductor Engineering, Inc. (ASE) and WUS Printed Circuit Co., Ltd. (WUS) announced today a strategic collaboration for the construction of a state-of-the-art manufacturing facility in the Nanzih Technology Industrial Park, Kaohsiung.