Fresh PCB Concepts: Key Considerations for Reliability, Performance, and Compliance in PCBs
Elementary Mr. Watson: Navigating RF—A Glide Path Approach to Design Success
Designers Notebook: Layer Stackup Planning for RF Circuit Boards
Silicon Valley Designers Council Chapter Meeting Oct. 13
October 5, 2016 | Silicon Valley IPC Designers CouncilEstimated reading time: Less than a minute
Join the Silicon Valley IPC Designers Council at TTM San Jose for an educational "Lunch 'n Learn" meeting on October 13 from 11:30 am to 1:30 pm. Speaker Julie Ellis, field applications engineer with TTM Technologies, will discuss “Printed Circuit Board Cost-Adders.”
A designer is faced with many challenges when planning their printed circuit board to achieve a balance of performance, quality and reliability versus cost. Unfortunately, the cost of a printed circuit board increases with size, thickness, number of layers, features, and technical difficulty.
Throughout this presentation, Julie will discuss basic design guidelines for standard production—as opposed to advanced capabilities—and how they affect the number of required processes and, therefore, cost. She will also discuss costs related to material utilization, fixed premiums for smaller lines/spaces and tolerances, and variable costs of high speed materials, drilling, and multiple lamination cycles. Lastly, Julie will show increasingly complex stack-ups to demonstrate how cost factors relate to the additional processes. You will learn the correlation between requirements and costs to help you make better design choices.
To RSVP, click here.
Location:
TTM San Jose
340 Turtle Creek Court
San Jose, CA 95125
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