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SHENMAO Technology to Present on No Clean Flux in Fine-pitch Flip Chip Interconnect at IWLPC 2016
October 11, 2016 | SHENMAO America Inc.Estimated reading time: Less than a minute
For several years, an approach to use fine-pitch flip chip package (<150um) with copper pillar/ micro-bump is for the realization of 2.5D/3D packages of higher density and performance enhancement. Generally, flux is widely used to clean the surfaces to be soldered for good wetting and form reliable joints. The upcoming concerns about fluxes are clean-ability for fine-pitch package, voiding and compatibility with underfill materials. There is a tradeoff between flux characteristics and soldering performance.
At the upcoming 13th International Wafer Level Packaging Conference (IWLPC), SHENMAO Technology Inc. will present a paper on a formulated no clean flux for fine-pitch flip chip package of copper pillar/micro-bump interconnect. This paper will discuss in details about the applicability of a new no clean flux in fine-pitch flip chip interconnect from the point of view of flux formulations, including flux activity for wetting performance, rheological characterization for the study of behaviors during reflow process and the evaluation of compatibility with underfill.
Authored by Hsiang-Chuan Chen, Ya-Ching Chuang, Chia-Hao Chang, and Watson Tseng, the paper will be presented during the Interactive Presentations session on October 18, 10:00 am to 1:30 pm.
Suggested Items
RF PCB Design Tips and Tricks
05/08/2025 | Cherie Litson, EPTAC MIT CID/CID+There are many great books, videos, and information online about designing PCBs for RF circuits. A few of my favorite RF sources are Hans Rosenberg, Stephen Chavez, and Rick Hartley, but there are many more. These PCB design engineers have a very good perspective on what it takes to take an RF design from schematic concept to PCB layout.
Trouble in Your Tank: Causes of Plating Voids, Pre-electroless Copper
05/09/2025 | Michael Carano -- Column: Trouble in Your TankIn the business of printed circuit fabrication, yield-reducing and costly defects can easily catch even the most seasoned engineers and production personnel off guard. In this month’s column, I’ll investigate copper plating voids with their genesis in the pre-plating process steps.
Elephantech: For a Greener Tomorrow
04/16/2025 | Marcy LaRont, PCB007 MagazineNobuhiko Okamoto is the global sales and marketing manager for Elephantech Inc., a Japanese startup with a vision to make electronics more sustainable. The company is developing a metal inkjet technology that can print directly on the substrate and then give it a copper thickness by plating. In this interview, he discusses this novel technology's environmental advantages, as well as its potential benefits for the PCB manufacturing and semiconductor packaging segments.
Trouble in Your Tank: Organic Addition Agents in Electrolytic Copper Plating
04/15/2025 | Michael Carano -- Column: Trouble in Your TankThere are numerous factors at play in the science of electroplating or, as most often called, electrolytic plating. One critical element is the use of organic addition agents and their role in copper plating. The function and use of these chemical compounds will be explored in more detail.
IDTechEx Highlights Recyclable Materials for PCBs
04/10/2025 | IDTechExConventional printed circuit board (PCB) manufacturing is wasteful, harmful to the environment and energy intensive. This can be mitigated by the implementation of new recyclable materials and technologies, which have the potential to revolutionize electronics manufacturing.