DesignCon Announces 2017 Awards for Best Papers

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The 2017 DesignCon Best Paper Award winners have been selected through a two-step review process. First, the DesignCon Technical Program Committee, which is comprised of leading experts in the electronic design space, reviewed all papers for impact, relevance, quality, and originality. The first-round finalists were then judged based on attendee feedback, collected at DesignCon 2017, on the impact of their presentation. 

"Congratulations to all finalists and winners of this year's Best Paper Awards. UBM is pleased to recognize these outstanding papers as the best of the excellent content that DesignCon offers its attendees," said Naomi Price, DesignCon Conference Content Director. "Each year, this awards program inspires engineers to strive to produce ground-breaking, top-tier content for the technical sessions at DesignCon."

Winning papers cover four categories of design: Chip-Level Design, Board/System-Level Design, Serial Link Design, and Power & RF Design. A list of the winners is below:

Chip-Level Design

Characterizing and Selecting the VRM, by Steve Sandler, Picotest

Board/System-Level Design

FastBER: A Novel Statistical Method for Arbitrary Transmitter Jitter, by Yunhui Chu, Alaeddin Aydiner, Kai Xiao, Beomtaek Lee, Oleg Mikulchenko, Adam Norman, Rob Friar, Charles Phares, Intel Corporation and Dan Oh, Samsung Electronics

Non-Destructive Analysis and EM Model Tuning of PCB Signal Traces using the Beatty Standard, by Heidi Barnes, Keysight Technologies; José Moreira and Manuel Walz, Advantest

RX IBIS-AMI Model Silicon Correlation Metrics and Model Development Methodology, by Masashi Shimanouchi, Hsinho Wu and Mike Peng Li, Intel Corporation

Serial Link Design

Exploring Efficient Variability-Aware Analysis Method for High-Speed Digital Link Design Using PCE, by Jan B. Preibisch, Torsten Reuschel, Katharina Scharff and Christian Schuster Technische Universität Hamburg-Harburg; Jayaprakash Balachandran and Bidyut Sen, Cisco Systems Inc.

Investigation of Mueller-Muller CDR Algorithms in PAM4 High speed Serial Links, by Yuhan Yao, Xun Zhang, Dawei Huang, Jianghui Su, Muthukumar Vairavan, and Chai Palusa, Oracle Corporation

PCIe Gen4 Standards Margin Assisted Outer Layer Equalization for Cross Lane Optimization in a 16GT/s PCIe Link, by Mohammad S. Mobin, BHaitao Xia, Aravind Nayak, Gene Saghi, Christopher Abel, Lane Smith and Jun Yao, Broadcom Ltd.

Power & RF Design

Cost-effective PCB Material Characterization for High-volume Production Monitoring, by Yongjin Choi, Christopher Cheng, Yasin Damgaci, Nagaraj Godishala, Hewlett-Packard Enterprise and Yuriy Shlepnev, Simberian

Overview and Comparison of Power Converter Stability Metrics by Joseph 'Abe' Hartman, Alejandro 'Alex' Miranda, Kavitha Narayandass, Alexander Nosovitski, and Istvan Novak, Oracle

RFI and Receiver Sensitivity Analysis in Mobile Electronic Devices, by Antonio Ciccomancini Scogna, Hwanwoo Shim, Jiheon Yu, Chang-Yong Oh, Seyoon Cheon, NamSeok Oh and Dong Sub Kim, Samsung Electronics Mobile Division, HE Group

Click Here to view the entire list of recipients, including individual researchers.

DesignCon 2018 Call for Papers
DesignCon returns to the Santa Clara Convention Center on January 30-February 1, 2018. Call for Papers will begin in mid-May with submissions due by the mid-July, 2017 deadline. To stay updated on next year's event, visit: designcon.com

About DesignCon
DesignCon is the world's premier conference for chip, board and systems design engineers in the high-speed communications and semiconductor communities. DesignCon, created by engineers for engineers, takes place annually in Silicon Valley and remains the largest gathering of chip, board and systems designers in the country.  This three-day technical conference and expo combines technical paper sessions, tutorials, industry panels, product demos and exhibits from the industry's leading experts and solutions providers. More information is available at designcon.com/santaclara.