14th Electronic Circuits World Convention

Estimated reading time: 8 minutes

Figure 5: Wearable devices 2015–2017 million of devices. (Source: Custer Consulting Group.)  

“Fan-Out Wafer-Level Packaging and 3D Packaging,” John Lau, ASM Pacific Technology 

John Lau was invited to do a four-hour tutorial on the latest advances and trends in semiconductor packaging technologies. I worked with John at HP Labs in the early 70s. He is a prolific author with 450 papers published and 18 books on 3D MEMS and IC integration packaging. 

This tutorial included fan-out/in wafer /panel-level packaging (FOW/PLP), 3D IC Integration with TSVs, 2.5D IC integration/TSV-less interposers. The detailed descriptions of these packages included: 

• Fan-in wafer-level chip scale packaging: used mainly for ICs with low pin-counts
• Fan-out waver level packaging: used with redistribution layers (RDL) to fan-out the circuitry beyond the chip edge without a lead-frame or substrate. There are three formations: Chip-First (Die-Up) also called eWLB (used for Apple’s A10 processor and by Samsung for the AP); Chip-First (Die-Down); Chip-Last (RDL-First); and Chip-First (RDL-First). Used for portables, mobile, and wearable products like baseband, RF switch/transceiver, PMIC, audio codec, MCU, and RF radar)
• Materials review like molding, RDL dielectrics, adhesives, conductors and sealants
• Internet of Things (IoTs)—priorities of cost, ultra-low power, small form factor and low heat dissipation
• Wafer-level system-in-package versus panel-level system-in-packages; WLSIP is a cost-effective way to build low-cost SIPs; PLSIP can increase throughput
• Memory chip stacking with TSV— used for memory capacity, low power consumption and wide bandwidth for high performance graphics, fast computations, MEMs, acoustic resonators, accelerometers and opto-electronics
• Package substrates for flip chips—TSMC/Xilinx’s CoWoS, Xilinx/SPIL’s TSV-less SLIT, SPIL/Xilinx’s TSV-less NTI, Amkor’s TSV-less SLIM, Intel’s TSV-less EMIB, ITRI’s TSV-less TSH, Shinko’s TSV-less i-THOP, Cisco’s/Samsung’s TSV-less organic interposer, Statschippac’s TSV-less FOFC-eWLP, ASE’s TSV-less FOCoS, Mediatek’s TSV-less RDLs by FOWLP and Sony’s TSV-less CIS. 

“Fan-out Packaging Innovations for Future,” Benson Lin, MediaTek 

Benson Lin opened by inventorying some of the upcoming challenges in the future: AI, gaming trends, virtual reality (VR), mobile devices, and automotive applications. These will all require higher performance advanced packaging characterized by: competitive costs, functional integration, more memory bandwidth and thinner, smaller substrates. Cost will continue to be king, as WL-Fan Out + RDL + TSV evolve. The challenges for WL packaging will be moving from wafers to panels, replacing bumps with TSVs, integrating multiple dies on the substrate, thinning dies and substrates with RDL, and meeting the density challenges to sub-micron by 2020 (Figure 6). The dielectric of the panel is unknown at this time.

Figure 6: The RDL on larger panels is the challenge that will determine costs for future packaging. 

“Updated FOWLP Development,” Shuzo Akejima, Storage & Electronic Devices Company, Toshiba 

Fan-out wafer level package (FO-WLP) has become the favorite for next-generation products like Apple’s A-10 PA that uses TSMC’s FOWLP (InFO). This invited talk was on further details of the FOWLP technology: 

• Description of the Apple A10 package
• Market size of approx. $6B, with materials being approximately $2.4B
• Future of TSMC’s InFO process vs. competing eWLP processes
• Issues with eWLP and the 12” wafer RDL. FOWLP evolution (Figure 7) and market growth for application processors like A10 to $7.6B by 2024
• Move to big panel mass production to meet needs of IoT, wearables and mobile; half the packages in smartphones are WLP (Figure 8).

Figure 7: FOWLP drew plenty of attention.                                                                         

Figure 8: FOWLP markets, products, present and future packages. (Source: Toshiba)      

“Four Essential Skills that Provided my Success in PCBs,” Happy Holden, I-Connect007 

Four of the 25 “Essential Skills” featured in my upcoming free e-Book, to be published by I-Connect007, were covered: 

• Problem Solving—one of the most important of skills for the process engineer, there are five main processes: TQC’s P-D-C-A; PI–PA Tools; the 8D Plan; the 7-Step Solution; and my favorite, Kepner-Tragoe Action Sequences (KT) (Figure 9).
• Design of Experiments—an essential skill that every process engineer needs to master problem solving and new process development. The most effective experimental tool and one that may take a lifetime to master all its intricacies. A free statistical tool box (the Engineering Statistical Handbook and s/w: DATAPLOT) are available for download here (Figure 10)
• Figure of Merit—the importance of metrics or measures of performance in problem solving and continuous improvement requires a consensus approach to determining new measures. I outline this unique process in the paper
• CIM/Automation Strategies—computer-integrated-manufacturing (CIM) and the new buzzword, Industry 4.0, require an automation planning methodology. I have defined a process to plan these strategies in an organized and cost efficient manner. Numerous examples were given for printed circuit fabrication including the most automated and newest PCB fab in the world (Figures 11 and 12).

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