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Cadence’s Sigrity Automates Power Integrity Simulation Earlier in Design Cycle
April 4, 2018 | Kelly Dack, CID+, EPTACEstimated reading time: 3 minutes
DesignCon is always a great place to check out the latest PCB layout and simulation software tools. During DesignCon 2018, I met with Sam Chitwood, a product engineer with Cadence. Sam explained how the Cadence Sigrity simulation software now allows users to make decisions early in the design process, and how this can help optimize the design of the power delivery network and ensure signal integrity in complex PCBs.
Kelly Dack: I’m here at DesignCon with Sam Chitwood. I understand that the Sigrity tools now address some power integrity methodology issues. Why don’t we start talking about power integrity by defining some of the problems that designers and engineers are facing?
Sam Chitwood: Power integrity has two different aspects, DC and AC. The first requirement is fundamentally supplying sufficient DC power to a device. Just like any mobile electronic device you’ve used in the past, you must have a battery—a DC power supply. DC issues can stem from a combination of high currents and insufficient routing metal.
AC power integrity can be considered from both the frequency and time domains. In the frequency domain, we strive for a flat impedance profile across the bandwidth of interest. In the time domain, consider the example of many I/Os that are switching. If their power source isn’t stable because it has a large amount of noise, that noise will manifest itself on those outputs as signal degradation. This phenomenon is known as simultaneous switching noise, or SSN, and shows how power integrity problems can cause signal integrity problems. Sigrity tools are special in that they can simulate signal, power, and ground together in both time and frequency domains.
Dack: Can simulation happen on the front end or the back end or both? Tell us where it’s best used.
Chitwood: Historically, most power integrity simulation have been post-layout, towards the end of a design cycle. And obviously, that’s where no one wants to be. Everyone is always running out of time, and there is almost never enough time to perform optimizations or a cost reduction. PI engineers barely have enough time to perform a signoff analysis to judge “pass or fail.”
What we’ve really tried to do over the past two years is what my colleague Brad Griffin likes to call “shift left.” That is, how can we move any type of analysis earlier—to the left—into the design cycle? Here is one example from a schematic point of view: Do you have enough decoupling capacitors on a rail? Do you have the correct decoupling capacitors on a rail? Most schematic designers today cannot answer those questions. Our goal has been to take what has historically only been done at the end-of-design cycle, a PI expert with barely enough time to do a check, and enable design engineers and layout engineers to assist much earlier. How can they participate?
Dack: Upstream, to me, means possibly the schematic level.
Chitwood: Yes, the goal is enabling schematic designers from the very beginning. This person needs an automated way of putting together something that is very simple and very quick but gives useful and actionable information. For example, have the correct decaps been selected? The schematic designer needs that information at the beginning, rather than have the PI expert at the very end say, “Oh, well, you had the wrong decaps all along.” Now you have to go back and rip this out, and it can be as bad as literally starting over from your power delivery routing point of view. Obviously, that’s tremendously expensive.
To read this entire interview, which appeared in the March 2018 issue of Design007 Magazine, click here.
SPONSORED LINKS
- Sigrity PowerDC Technology
- How Your PCB Design Team Can Become Your Dream Team for Power Integrity
- How a Team-Based Approach to PCB PI Analysis Yields Better Results
- Sigrity Tech Tips
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