Fresh PCB Concepts: Key Considerations for Reliability, Performance, and Compliance in PCBs
Elementary Mr. Watson: Navigating RF—A Glide Path Approach to Design Success
Designers Notebook: Layer Stackup Planning for RF Circuit Boards
Mentor’s HyperLynx Automates SERDES Channel Design
April 9, 2018 | Andy Shaughnessy, Design007 MagazineEstimated reading time: 2 minutes
Mentor recently released the newest version of its HyperLynx signal integrity software. This version may be the first SI tool in the industry to fully automate SERDES design channel validation. I spoke recently with Chuck Ferry, product marketing manager with Mentor, about the new HyperLynx and some of the new serial link design capabilities that customers have been demanding.
Andy Shaughnessy: Some of the newer HyperLynx capabilities are focused on the users’ SERDES design challenges. Part of the problem with SERDES seems to be that the standards for SERDES have been playing catch-up for a while, according to quite a few design engineers. What do you see going on in the SERDES standards space?
Chuck Ferry: SERDES-related standards have been evolving very quickly. The number of protocols for high-speed serial data has increased drastically in the last few years. Often with each new generation of protocol, the data rates are doubling. Some of the challenges hardware designers face with the recent protocols are related to differences in the types of analysis that are required and the results they must understand to properly determine if a interface will pass or fail the requirements for that given protocol. For example, the new standards rely on new metrics such as channel operating margin (COM) to determine the pass or fail criteria of the interconnect.
Shaughnessy: What does it take to validate high-speed serial interface from chip-to-chip in a large system? It seems that it would be a real issue with a data center or cellular base station.
Ferry: To validate a high-speed serial link end-to-end per modern protocol every aspect of the signal interconnect between the chips must be modeled accurately including the IC packages, trace interconnect, as well as the characteristics of the drivers and receivers, including complex equalization schemes and optimization capabilities associated with those.
Shaughnessy: What questions are you hearing from hardware designers who are tackling these types of designs?
Ferry: The latest version of HyperLynx's new capabilities provides solutions to system-level designers with hard questions along these lines. They’re wondering, “Are my implementations possible with various physical constraints and selected board materials? What if I don't have models for my driver or don't know what driver will be, but I just know the standard that it needs to comply to? How can I quickly validate an interface with this specific protocol standard? How can I model this long interconnect channel with 3D features in a reasonable amount of time? How can I find problems in my channel design before it's actually full routed?”
To read this entire article, which appeared in the March 2018 issue of Design007 Magazine, click here.
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