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Beyond Design: AC/DC is Not Just a Rock Band

To eliminate the excess parasitic capacitance, associated with surface mount lands, a portion of the reference plane, that is directly beneath the component, should be removed. This allows the signal that traverses through the capacitor to reference a lower plane (further away) and reduces the parasitic capacitance, thereby minimizing the impedance mismatch. This principle should also be applied to surface mount connectors if present in the path (Figure 3).

Figure 3: AC coupling capacitors (left) with plane cut-outs and GND vias (right).

On the left there are two capacitors which are referenced to the plane on layer 2. Whereas, the picture on the right shows the optimized structure with the plane cut-outs included. The lands then reference to the layer 3 plane increasing the impedance. The board stackup and trace geometries (Figure 4) are designed to provide a 100 Ω differential signal. All traces and plane layers are 1 oz. copper. The width of the surface mount lands is set to 20 mils to match the width of the 0402 type capacitors. And, the length of the cut-out is equal to the end-to-end distance of the two surface mount lands. The iCD Stackup Planner can be used to estimate the impedance, to the lower plane on layer 3, by swapping the layer 2 plane for a signal layer as depicted. This increases the impedance from 72 to 100 Ω.

The four ground vias near the AC coupling capacitors and the two on the connector lands, in Figure 3, are essential to provide a direct current return path to the lower GND plane and back. Vias correctly placed will serve to minimize crosstalk and contain the common modes that propagate due to signal skew. Common-mode conversion near the receiver can have some disastrous multi-aggressor crosstalk peaking implications.

Figure 4: 100 Ω impedance when the plane beneath the capacitor is removed (source: iCD Stackup Planner).

Figure 5 shows a TDR impedance plot from an Ansoft HFSS simulation. The red line is the impedance profile of the high-speed differential traces without the plane cut-out under the surface mount lands of the AC coupling capacitors. The other lines are the impedance profiles with the cut-out set to different widths.

The simulation results show that the width of the plane cut-out plays an important role in minimizing the impedance mismatch. The impedance without the plane cut-out is below 75 Ω at the capacitor lands. However, this needs to be increased to 100 Ω to avoid reflections. The minimum impedance mismatch and therefore the optimum structure is achieved when the width of the cut-out is 25 mils. For most applications, a capacitance value of 100 nF with a 0402 package, for the AC coupling capacitor, is adequate.

Figure 5: TDR simulation of impedance profile vs plane cut-out width (source: Altera).

This is a basic guideline to follow if you do not have access to a simulation tool. If the lower plane is a power plane or if there is no lower plane, a ground fill can be poured in the region underneath the capacitors and stitched with four GND vias close to each capacitor land. 

On the other hand, a more elegant alternative is to use a smaller capacitor such as an 01005. The explicit assumption (above) is that capacitor land width exceeds the trace width and hence represents a short section of transmission line that requires a cut-out to maintain impedance. However, an 8 mil trace can be used in conjunction with an 01005 package of 8 mil land width to avoid the impedance mismatch altogether. In this case, the cut-out is not required. This is a superior solution as the loss is not frequency-dependent. Cut-outs are a curse on our dependence on thin traces.

Key Points

• Discontinuities in the physical geometries, along the transmission path, degrade the signal by loss of amplitude, reduction of rise time, and increased jitter.
• A capacitor is typically placed in series with both differential signal traces to remove common mode voltage differences.
• AC coupling is useful because the DC component of a signal acts as a voltage offset, and removing it can increase the resolution of the signal and allows different technologies to communicate.
• The most important parameter of the AC coupling capacitor is the relative geometry with respect to its environment.
• It does not matter where an AC coupling capacitor is placed along the transmission path.
• The capacitor transition is critical: how low the reflectivity is, and whether it is placed near other channel discontinuities.
• AC coupling removes the common mode level and allows the receiver to set its own bias point.
• To eliminate the excess parasitic capacitance, associated with surface mount lands, a portion of the reference plane, that is directly beneath the component, can be removed.
• Ground vias placed near the AC coupling capacitors are essential to provide a direct current return path to the lower GND plane and back.
• The minimum impedance mismatch and therefore the optimum structure is achieved when the width of the cut-out beneath the capacitor is 25 mils.
• For most applications, a capacitance value of 100 nF with an 0402 package for the AC coupling capacitor is adequate.

 References

1. DC Coupling with 7 Series FPGAs GTX Transceivers, Xilinx.
2. Optimizing Impedance Discontinuity Caused by SM Pads for High-Speed Channel Designs, Altera.
3. AC and DC Coupling: What's the Difference? Siemens.
4. High-Speed Digital Design, Howard Johnson.

Barry Olney is managing director of In-Circuit Design Pty Ltd (iCD), Australia, a PCB design service bureau that specializes in board-level simulation. The company developed the iCD Design Integrity software incorporating the iCD Stackup, PDN and CPW Planner. The software can be downloaded from www.icd.com.au. To contact Olney, or read past columns, click here.

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