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Current power demands are increasing, especially with AI, 5G, and EV chips. This month, our experts share “watt’s up” with power integrity, from planning and layout through measurement and manufacturing.
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If you don’t have signal integrity problems now, you will eventually. This month, our expert contributors share a variety of SI techniques that can help designers avoid ground bounce, crosstalk, parasitic issues, and much more.
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Cadence Webinar: Preventing EMC Problems in IC Package and PCB Designs
March 8, 2019 | Cadence Design Systems, Inc.Estimated reading time: Less than a minute
EMC compliance is required by all commercial electronic devices to ensure safety, compatibility, and reliable operation.
Cadence Sigrity technology provides fast and accurate design analysis and performance verification without the need of a physical prototype—giving you powerful early issue detection and streamlined resolution.
Join Cadence Education Services and signal integrity/power integrity (SI/PI) expert Srdjan Djordjevic on March 14, 2019, 16:00 CET, for a free one-hour live webinar to find out what SI/PI analysis tools can do for you.
The webinar will show you how to include EMC simulations and analysis early in the design stage to help avoid costly redesigns. The demo utilizes the Sigrity PowerSIand OptimizePI (frequency domain) tools to show how SI/PI analysis supports EMC analysis and uses post-processing steps to identify radiated emissions.
Cadence Sigrity technology supports all layout systems (Mentor, Zuken, Altium, Cadence Allegro, Cadence SiP, Cadence Allegro Package Designer, and others)—giving you maximum flexibility with optimal compatibility.
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