-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueTraining New Designers
Where will we find the next generation of PCB designers and design engineers? Once we locate them, how will we train and educate them? What will PCB designers of the future need to master to deal with tomorrow’s technology?
The Designer of the Future
Our expert contributors peer into their crystal balls and offer their thoughts on the designers and design engineers of tomorrow, and what their jobs will look like.
Advanced Packaging and Stackup Design
This month, our expert contributors discuss the impact of advanced packaging on stackup design—from SI and DFM challenges through the variety of material tradeoffs that designers must contend with in HDI and UHDI.
- Articles
- Columns
Search Console
- Links
- Media kit
||| MENU - design007 Magazine
3DEM Modeling: Influence of Metal Plating on PCB Channel Loss and Impedance
March 21, 2019 | Chang Fei Yee, Keysight TechnologiesEstimated reading time: 1 minute

This article briefly introduces different types of metal plating commonly used in PCB fabrication. Subsequently, the influence of metal plating on PCB channel loss (i.e., insertion loss or S21) and impedance (i.e., time domain reflectometry or TDR) is studied with 3DEM modeling using Keysight EMPro.
Introduction
Metal plating that serves as a protective layer is applied on top of the copper traces during PCB fabrication, thus alleviating the oxidation process of the copper. Common finishes include immersion silver (IAg), electroless nickel immersion gold (ENIG), etc. With immersion silver, nearly pure silver (i.e., ~0.02 mils in thickness) is coated over the copper traces on a PCB. Meanwhile, with ENIG, nickel (i.e., ~0.2 mils in thickness) is deposited on the copper trace followed by a coating of gold (i.e., ~0.01 mils in thickness) on top. Nickel serves as a barrier layer to prevent the migration of gold into the base copper.
However, metal plating comes with disadvantages. On a PCB, the current of the signal tends to propagate more closely to the surface of the trace when the frequency of the signal becomes higher. Skin depth is the parameter that determines how extensive the current of signal travels with reference to the surface of the transmission channel. The relationship between skin depth and signal frequency is governed by Equation 1. For instance, at frequency 10 GHz, skin depth becomes 0.026 mils.
Equations 2, 3, and 4 indicate that attenuation of the signal is inversely proportional to the metal conductivity. Once metal with lower conductivity is coated over a copper trace, the signal experiences a larger amount of attenuation. For instance, skin depth becomes 0.026 mils at a signal frequency of 10 GHz. If ENIG plating (i.e., base copper 1.09 mils, nickel 0.2 mils in the mid layer, and gold 0.01 mils on top) is applied, the high-frequency signal will propagate on the gold and nickel-plated layers. This signal will encounter a larger magnitude of attenuation due to the lower conductivity of nickel.
To read this entire article, which appeared in the February 2019 issue of Design007 Magazine, click here.
Suggested Items
EIPC 2025 Winter Conference, Day 2: A Roadmap to Material Selection
02/20/2025 | Pete Starkey, I-Connect007The EIPC 2025 Winter Conference, Feb. 4-5, in Luxembourg City, featured keynotes and two days of conference proceedings. The keynote session and first-day conference proceedings are reported separately. Here is my review of the second day’s conference proceedings. Delegates dutifully assembled bright and early, well-rested and eager to participate in the second day’s proceedings of the EIPC Winter Conference in Luxembourg.
Designers Notebook: Addressing Future Challenges for Designers
02/06/2025 | Vern Solberg -- Column: Designer's NotebookThe printed circuit board is and will probably continue to be the base platform for most electronics. With the proliferation of new generations of high I/O, fine-pitch surface mount semiconductor package variations, circuit interconnect is an insignificant factor. Circuit board designers continually face challenges such as component quantity and complexity, limited surface area, and meeting the circuit board’s cost target. The printed circuit design engineer’s prominent position demands the development of efficiently manufacturable products that perform without compromise.
DesignCon 2025, Day 2: It’s All About AI
01/30/2025 | Marcy LaRont, I-Connect007It’s hard to get away from the topic of artificial intelligence, but why would you? It’s everywhere and in everything, and my time attending presentations about AI at DesignCon 2025 was well worth it. The conference’s agenda featured engaging presentations and discussions focused on the technological advancements in AI, big data centers, and memory innovations, emphasizing the critical relationship between processors and circuit boards.
Beyond Design: Electro-optical Circuit Boards
01/22/2025 | Barry Olney -- Column: Beyond DesignPredicting the role of PCB designers in 10 years is a challenge. If only I had a crystal ball. However, we know that as technology progresses, the limitations of copper PCBs are increasingly apparent, particularly regarding speed, bandwidth, and signal integrity. Innovations such as optical interconnects and photonic integrated circuits are setting the stage for the next generation of PCBs, delivering higher performance and efficiency. The future of PCB design will probably incorporate these new technologies to address the challenges of traditional copper-based designs.
Designers Notebook: Impact of Advanced Semiconductor Packaging on PCB Stackup
01/07/2025 | Vern Solberg -- Column: Designer's NotebookTo accommodate new generations of high I/O semiconductor packaging, printed circuit board fabrication technology has had to undergo significant changes in both the process methods and the criteria for base material selection and construction sequence (stackup). Many of the new high-function multi-core semiconductor package families require more terminals than their predecessors, requiring a significantly narrower terminal pitch. Interconnecting these very fine-pitch, high I/O semiconductors to the PCB is made possible by an intermediate element referred to as an interposer.