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The 16th Annual International Wafer-Level Packaging Conference (IWLPC), which brings together some of the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging and manufacturing, will be held on October 22–24, 2019 in San Jose, California, USA.
Interconnecting wafer-level packaging, 3D packaging, and advanced manufacturing and test, the IWLPC is at the forefront of the packaging technology evolution.
The Wafer-Level Packaging (WLP) track features sessions on advanced wafer level packaging and materials, reliability and metrology, fan out wafer level packaging (FO-WLP), and advanced processing.
The 3D Packaging track features sessions on design, characterization and test, wafer bonding and chip stacking, and processing for fan-out.
The Advanced Manufacturing track features sessions on process materials and equipment.
To register for the IWLPC, click here: https://www.iwlpc.com/register_now.cfm.
