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This month, our expert contributors discuss the impact of advanced packaging on stackup design—from SI and DFM challenges through the variety of material tradeoffs that designers must contend with in HDI and UHDI.
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Keysight Webinar May 6: Get Ready for Gen5 With PCIe and DDR
April 23, 2020 | Keysight TechnologiesEstimated reading time: Less than a minute
This Keysight seminar will be held May 6, 2020. Presenters will cover test and validation methodologies, with best-practice examples, to help PCIe 5.0 and DDR5 technology adopters fully test all key measurement parameters to ensure their design meets the specification requirements.
Attendees will learn the following:
- Evolution of PCIe and DDR technologies
- PHY Layer testing challenges at 32 GHz NRZ and 64 GT/s
- Looking forward to PAM4 technologies
- TX and RX test solutions for PCIe 5.0 and DDR5 Devices
- Simulation and verification environments
- New requirements for DDR5 simulation
AGENDA
- 10:00 am PT / 1:00 pm ET
Leading Edge + Mainstream Technologies: Everything is Moving to Next Generation - 10:30 am PT / 1:30 pm ET
Master PCIe Transmitter and Receiver Measurement Techniques - 11:45 am PT / 2:45 pm ET
Latest DDR5 Developments – Planning for DDR6
For a more detailed agenda, please click here.
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