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July 7, 2020 | I-Connect007 Editorial TeamEstimated reading time: 1 minute
We asked for you to send in your questions for Happy Holden, and you took us up on it! The questions you've posed run the gamut, covering technology, the worldwide fab market, and everything in between. Enjoy.
Q: For space applications (without air), how should we calculate external layer current-carrying traces against the IPC-2221 (formerly IPC-D-275) charts?
A: I have never studied that, so I turned this question over to an expert, my friend Mike Jouppi, former committee chair of IPC-2152 Standard for Determining Current Carrying Capacity in Printed Board Design. This standard will provide many answers to your questions. Mike wrote Chapters 22 and 23 in the seventh edition of the Printed Circuits Handbook, edited by Clyde F. Coombs and me.
Mike answered: I'm a mechanical engineer who worked as a career thermal analyst. The charts in IPC-2152 in almost all cases will be conservative (both air and vacuum environments). The vacuum is for space environments. The purpose behind these charts is misconstrued by most users. My intention when they were developed was to use these charts as a baseline for developing thermal models that could be used to better understand the actual temperature rise of conductors in actual designs, which I did for my own design purposes. The concept did not catch on.
There is a significant difference between the temperature rise in a conductor, tested per IPC-TM-2.5.4.1a, and most PWB design configurations. The reason is that most designs have copper ground and power planes that conduct energy away from the traces. In addition, most designs in space applications have a significant conduction path from the PWB through-bolted fasteners or wedge locks to a sink.
Since the question does not include IPC-2152, I would recommend researching IPC-2152 and accounting for the power dissipations in the traces in the thermal design. I also recommend accounting for the conductor power dissipation in all designs, especially if the designers are not familiar with sizing parallel conductors. Parallel conductors are easily managed with accounting for conductor losses (power dissipation). FYI: It was the power dissipation in conductors that motivated me to lead the development of IPC-2152.
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