IBM Awarded Best Technical Paper at IPC APEX EXPO 2021

Estimated reading time: 3 minutes

Nolan Johnson and Happy Holden speak with Sarah Czaplewski, whose team at IBM won the Best Technical Paper award at this year’s IPC APEX for “Signal Integrity, Reliability, and Cost Evaluation of PCB Interlayer Crosstalk Reduction.”

Nolan Johnson: Sarah, you and your team were selected as the best technical paper for IPC APEX 2021. Would you be so kind as to start us off with an introduction to your team?

Sarah Czaplewski: Sure. There are three of us on the paper. Besides myself there is Junyang Tang and Roger Krabbenhoft.  Junyan Tang is an IBM signal integrity engineer based in Austin, Texas, and was primarily responsible for the signal integrity modeling and analysis portion of the paper. Roger Krabbenhoft is an IBM STSM and lead PCB technologist located in Rochester, Minnesota. Roger contributed the PCB supplier cost and yield impact section and suggested the items we evaluated as part of the IBM PCB roadmap. I am a PCB qualification and reliability engineer and I was responsible for the reliability portion of the paper.

Johnson: What motivated this research?

Czaplewski: We’re working on the next generation of products and we need a little bit more signal integrity improvement. One of the levers to pull is to make some adjustments within the PCB design. So that’s why we evaluated at reduced layer-to-layer misregistration and reduced antipad diameter around backdrill PTHs. This research is preparing us for the future product generations.

Johnson: Walk us through the paper, which is titled, “Signal Integrity, Reliability, and Cost Evaluation of PCB Interlayer Crosstalk Reduction.”

Czaplewski: The push for higher data rates and more functionality is leading to higher density in PCBs, which increases the opportunity for crosstalk. We’re looking to mitigate that. We modeled the signal integrity impacts of reducing layer-to-layer misregistration from five mils, down to four and three mils. We also looked at reducing the antipad diameter in the backdrilled regions of PTHs from 30 mils on a 10 mil finished PTH to 28 mils.  As one reduces the antipad diameter on the backdrilled holes, there is an increased risk of exposing the planes during the backdrill operation, which can cause a wide range of reliability issues. In the reliability portion of the paper, we sought to understand that by intentionally exposing the planes. We had some of the backdrilled holes filled with resin to evaluate if that would have an impact on reliability. These reduced layer misregistration and reduced antipad diameter are going to impact the yield at the PCB manufacturer. So we also conducted manufacturer polling to get a relative cost impact of our two proposed changes to create a cost benefit analysis.

Johnson: I found it quite interesting that the two different solutions—misregistration as well as reducing the diameter of the antipads—are both intended to get more precise and more condensed board fabrication. You’re pushing tolerances closer to zero in both cases.

Czaplewski: Correct.

Johnson: Walk us through what you found.

Czaplewski: I’ll start with the reliability part because that’s my expertise area. I expected to have electrochemical migration or some sort of corrosion forming between biased planes within the backdrilled holes, but surprisingly we did not detect any fails in the unfilled holes. We actually had some fails in the filled holes, which was opposite of what we were expecting. We’re still investigating this, but we’re thinking it’s related to the hole fill process and potentially the hole clean process before resin fill. That was an interesting finding and something that needs to be investigated more before implementing reduced antipad diameters, which, with manufacturing tolerances, can result in plane exposure.

To read this entire interview, which appeared in the 2021 edition of Show & Tell Magazine, click here.