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PCB Talk: A Review of Additive Electronics

Additive electronics, particularly as it pertains to PCB fabrication processes, is garnering a lot of attention. The ability to form much tighter feature sizes than typically available from subtractive etch PCB fabrication processes, along with significant RF benefits, is opening new possibilities for PCB designers as they work to navigate the increasingly complex balance between functionality, size, and complexity. As with any new technology, there is a learning curve for PCB designs. This is the second in a series of columns intended to shed light on the experience these early adopters have gained. Here, I speak with Tomas Chester, founder and hardware designer for Chester Electronic Design.

Tara Dunn: Tomas, you are a well-known designer and instructor in the industry, but for those who have not had the opportunity to meet you, could you please start with a quick introduction? 

Tomas Chester: Sure. I am a hardware design engineer from Ontario, Canada. In 2017, I founded my own contracting and consulting firm, Chester Electronic Design. Since then, I have worked on all manner of boards from IMS to semi-flex. In 2020, I started the Ontario Canada PCEA Chapter, and in 2021, I joined the PCEA Executive Board. I am also a full-time Altium instructor for their Essentials and Advanced courses.

Dunn: That is an impressive resume. I am positive that founding your own contracting and consulting firm requires you to have knowledge in many different types of technology. One thing you and I have talked about quite a bit is the potential benefits of using 25-micron trace and space or below in PCB design. What were some of your initial thoughts? What caught your eye?

Chester: My initial thought jumped to the possible use cases in those ultra-small design cases. I can see a lot of uses for technology like this in the medical space or even in the wearable devices market. Being able to have such small traces is going enable not only smaller designs, but higher utilization of existing real estate, which will lead to the reduction of raw materials required to build a design.

Dunn: You had a few questions early in our discussions that I think are going to be common questions among PCB designers.

Chester: What trace-to-trace gap distance is possible? 

Dunn: With the right photolithography set-up as small as 12.5 microns has been run. Most fabricators can do 20 to 25 microns.

Chester: As this is an additive process, how tall of a trace can you get? Can you control this height?

Dunn: Currently, for a 25-micron (.001”) line, a 20 to 25 micron (.0008” to .001”) thick line is standard with 50 microns (.002”) possible but not tested. On a 50-micron line, a 50-micron thickness can be done.

Chester: How tight is the line-width control?

Dunn: This is very tight, typically ±1 micron (±.000039”).

Chester: Do you need to use a special solder mask when using a very fine pitch semi-additive design process?

Dunn: No. Typically, the design will end up with an LDI imageable mask, but that is very common now. Consideration needs to be given to mask-defined pads over copper defined to keep the adjacent traces covered.

Chester: Where in the design fabrication process does this fit?

Dunn: The semi-additive process is completed early in the fabrication process. To over-simplify, where traditional subtractive etch processes start with a copper-clad laminate panel and etches away the copper that is not required, the semi-additive approach begins with the base dielectric and adds copper to the panel in only selected areas. 

Chester: Can you mechanically drill with SAP, or do you need to use a special drilling process?

Dunn: Both mechanical drill and laser drill can be used with semi-additive processes.

Dunn: We are just scratching the surface on how best to apply these new fabrication capabilities to PCB design. There are obvious benefits to overall size and weight. There is also the potential to reduce layer count, reduce lamination cycles, and reduce the number of microvia layers needed, which all increase yield and overall reliability. What aspect of these new PCB fabrication capabilities is most valuable to you?

Chester: I think all designers are going to be excited with the ability to access some of these benefits. For me personally I am excited about the ability to breakout of the µBGA part without needing to do other HDI design strategies.

Dunn: You are currently working on a project that involves redesigning an Altium reference design, applying 25-micron trace/space where it makes sense. Can you tell us about the project?

Chester: To get a better understanding of some of the requirements and difficulties a designer would need to design an SAP product, I am using an existing Altium DDR4 SODIMM design to reimagine it utilizing SAP. This is resulting in some promising improvements with respect to layer reduction and it also has reduced the overall complexity of designing a DDR4 fly-by architecture. As with any engineering process, there are some assumptions that have been made with respect to the design as we are still in the early days of SAP, so this is intended as a learning and educational piece with an understanding that it may not be functional. However, as I said, it is more about the experience and getting that key information on how to implement SAP into a design and what improvements come out of it. The key in this situation is having an existing design that we can refer to and compare the changes once we complete the design.

Dunn: I am looking forward to those results. Working with something new can be exciting and just a little intimidating. In navigating the learning curve, do you see any challenges for designing with this new technology in mind?

Chester: I think that there are some challenges that will need to be overcome. Due to the changes in trace size and with respect to how new this process is, the impedance and the field theory around using this in a design is still being developed. The SAP process means we are shifting away from planar coupling of traces and starting to deal with broadside coupling and the requirements for co-planar wave guides. Currently there is no proper way to calculate what this is going to do at such a small scale, which could cause all sorts of design and signal integrity issues.

Dunn: Tomas, as we wrap up, what advice would you give to PCB designers who are just hearing about the opportunity to work with fabricators that can now offer these fine feature sizes?

Chester: Get in touch with your fabricator as early as possible and make sure you discuss this with them. They will have all kinds of insight on what to do and having them review your design as you progress will increase the chances of a Revision A success. They will also be able to give you additional details of their capabilities and any issue areas they have encountered on other previous designs.

Dunn: Thank you so much for talking with me today.

This column originally appeared in the June 2021 issue of Design007 Magazine.