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PCB Talk: Pin-Out Challenge—Re-think the Solution

Semi-additive PCB fabrication is getting a lot of attention as fabricators install new processes that enable them to provide much finer features than traditional subtractive etch processes. This is opening new opportunities and tools for PCB designers to solve today’s complex electronics challenges. These packaging and interconnect solutions can reduce size and weight by 90% over traditional processing techniques in the U.S. and bring significant signal integrity benefits. As with any new technology, there are many questions: How to apply this new capability to the design, what are the signal integrity considerations, and who has the capability to supply these fine features?

This column kicks off a series of interviews with veteran PCB designer who share their thoughts, opinions, and questions as they navigate this new frontier. I recently sat down with Cherie Litson, MIT CID/CID+, president of Litson1 Consulting and an instructor at Everett Community College, to understand her perspective on this new fabrication capability.

Tara Dunn: Cherie, you are a well-known designer and instructor in the industry, but for those who have not had the opportunity to meet you, could you please start with a quick introduction? 

Cherie Litson: My background is broad and deep: it has been an amazing opportunity to work with so many companies, notably Microsoft—where I helped create their design database for the Surface and, earlier, the first wireless mouse. The first hand-held ultrasound from SonoSite was another passion project. Passing on what I have learned from others led me to become a Master Instructor for the IPC Designer Certification program. I learn more every time I teach. As a member of the Averatek Community of Interest, I encourage everyone in the industry to share their experiences with this new technology so we can all learn and optimize the benefits of new developments.

Figure 1: Cherie Litson is an instructor at Everett Community College.

Golf is my other passion: I have been involved in the LPGA Amateur Association (previously EWGA) since 2001. While learning how golf and the professional world mix, I have been able to take my golfing teams from local to national competitions for the past five years. I could go on about golf, but let’s tee up this discussion!

Dunn: Impressive! My golf skills stop with my highly developed golf cart driving expertise; actually hitting that ball in a straight line is something I am still working on. You mention Averatek’s Community of Interest; this is new. Can you tell me about that?

Litson: Averatek, a Silicon Valley innovation company, manufactures key chemistries and licenses the processes for their use. Two processes, in particular, are having an effect on the PCB design industry: LMI^TM, the catalytic ink used in the A-SAP™ process, and Mina™, a surface treatment that enables soldering to aluminum. These products are now commercially available through licensed fabricators, so it is important for designers to learn about them. The Community of Interest is starting to bring together a wide range of people from all sectors of the industry who are interested in learning more about semi-additive PCB processes. Nothing formal yet, but we're hoping to set up a website or blog to pool our knowledge on these types of products.

Dunn: What aspect of these new PCB fabrication capabilities is most valuable to you?

Litson: I am excited by the ability to route traces at 1 mil or even below, as that opens possibilities for designers to produce increased density at lower cost. The A-SAP process provides the designer an opportunity to significantly reduce layer count, simplifying complex designs. 

These geometries can potentially eliminate pin-out challenges while maintaining reliable signal integrity. I can see the advantages of using a taller yet narrower trace for signal integrity; this is the winning factor for me. This process results in traces with vertical rather than trapezoidal sidewalls, realizing benefits in both size and RF advantages, eliminating the etch compensation requirements.

Designers working on next-generation products will be excited about the ability to form a 15-µm trace and space with the semi-additive processes. Many designs are being driven to require line and spaces at 50 µm due to smaller pin spacing on components and smaller package products. The fabrication of these traces is something that has not been available in the U.S. until now.

Dunn: Cherie, I know you are an avid learner; when you are researching new technology, which reliability tests mean the most to you?

Litson: As I consider how to best apply this technology, material compatibility is an important aspect. It is important to know that a new process is going to be compatible with nearly all materials. Next, I’m looking into the electrical aspects of these new geometries.

I also look at proven reliability parameters: the A-SAP process passed peel strength, IST coupon testing, and signal integrity analysis across a variety of materials.

Dunn: Working with something new can be exciting and just a little intimidating. Navigating the learning curve, do you see any challenges for designing with this new technology in mind?

Litson: In my opinion, designers should remember their basic electronics—it influences everything we do. We must understand the physics to make certain we know what will be affected. With these new parameters, we will need to go back and take another look at our calculations, which are based on the resistance of copper which is based on the area. Then bring into the equations the resistance of the dielectric materials, layer structures, etc. I am curious to see how the geometry of the conductors shifts the electrical results.

Because each product is different, there are few set-in-stone design rules for semi-additive processed layer-only guidelines. The most important guideline: this process requires close collaboration between design and fabrication. For additional guidance, a collection of case studies would be great, maybe online as a dynamic design guide. Just brainstorming!

Dunn: An online dynamic design guide is a great idea. Taking a step back from design, why do you feel that this new technology is important to the industry?

Litson: I think this is important to the industry for several reasons. One is implementation of this process—it is designed to integrate with existing PCB fabrication equipment, so it does not require the costly capital investment usually associated with new technologies, allowing even the smaller and mid-size shops to offer this advanced technology to their customers.  

While this process certainly gives us the benefit of 25 µm line/space and below, the additive process also has RF benefits at larger feature sizes, such as improving impedance control. I think we are just scratching the surface of how to get the most benefit from this capability. I am already seeing the simplification of complex designs, improving yields, and reducing costs. I am excited to see where this technology takes us. 

Dunn: Cherie, as we wrap up, what advice would you give to PCB designers who are just hearing about the opportunity to work with fabricators that can now offer these fine feature sizes?

Litson: Start today! Do some research, share your concerns, share your experiences, try it out. I can see many benefits to utilizing this process at the 75 µm, 50 µm, and 25 µm trace sizes and smaller.

Dunn: Thank you so much for talking with me today. To learn more, what is the best way to reach you?

Litson: The best way to reach me is at Litson1@aol.com. Thank you.

This column originally appeared in the May 2021 issue of Design007 Magazine.