Estimated reading time: 4 minutes

Trouble in Your Tank: Processes to Support IC Substrates, Advanced Packaging—Part 1

Introduction
There has been much written and discussed over the last 18 months relating to semiconductor fabrication and the well-founded concerns that the U.S., in particular, has fallen behind in domestic chip manufacturing. In response to this issue, the U.S. government has enacted the CHIPS and Science Act. Funding under this legislation is designed to drive more chip fabrication domestically. While this is all fine and good, once these advanced chips are manufactured, where will they go? As has been said ad nauseum, “Chips don’t float.”

These chips require packaging and, in turn, advanced PWBs to support those packages. The PWB and the IC substrates are the physical platform to which these chips, micro-processers, capacitors, memory, logic, etc., are mounted and interconnected. Without a high-reliability, high density platform, the chips have nowhere to go. This is precisely why critical technologies, processes, and materials must be adopted to support chip production and advanced packaging.

The subject of this month’s column is to delineate critical areas in which fabricators in the PWB world must both embrace and master to support advanced packaging. These are:

• Tooling and materials selection
• Small hole drilling/via formation
• Desmear and metallization
• Advanced photolithography and fine-line etching
• Blind-via plating/blind and buried via hole fill
• Signal integrity
• Quality control and qualifications

Part 1 of this article will focus on the following areas:

• Tooling and materials selection
• Small hole drilling/via formation
• Desmear and metallization

Tooling and Materials Selection
HDI boards are characterized by smaller features and tighter registrations. To this end, feature compensation and scaling are much more important than on regular boards. HDI boards are also used for high-frequency applications, and thus, solving these demands creates new challenges for an engineering/tooling department. Table 1 shows three major challenges in engineering high-frequency boards.

Materials selection is equally important, especially because of lead-free assembly temperatures and their effect on laminate delamination and reliability. Important new capabilities to embrace are:

1. Impedance calculations and stackups for high-frequency boards using “co-planar waveguides” and co-planar stripline models.
2. Characteristics and scaling/feature compensation for the newer phenolic-epoxy and halogen-free FR-4s.
3. Ability to add local fiducials to align laser drilling CCD cameras.
4. System to store laser drilling parameters based on diameter, depth, and materials types.
   1. Characteristics of via-plugging to determine if placement of buried vias will create problems¹.

From a materials standpoint, low Dk and low loss laminate materials are the laminates of choice. Signal integrity and impedance matching are required. Minimizing signal loss at high frequencies is paramount to IC substrate technology that supports advanced packaging. This brings one to gain a better understanding of via formation and desmear/metallization.

Small Hole/Microvia Formation
Although HDI is normally associated with laser drilling, small blind vias can also be formed by mechanical drilling and chemical etching. What’s important is a process that guarantees each board will receive the correct microvia drilling parameters. Ideally, the shape of the formed via will show a wider opening at the top of the via before gradually tapering down (Figure 1).

The shape of the via is critical to enable uniform copper plating. The fluid dynamics of the plating operation require the constant replenishment of key plating additives to ensure that fresh electrolyte is exchanged to reduce concentration polarization. With concentration polarization, the diffusion layer is starved of copper ions and other additives.

A non-ideal via formation is shown in Figure 2. Note that the diameter of the blind via is slightly narrower at the top. In addition, the quality of the overall via is compromised, as evidenced by the excessive removal of the adhesive material. With a situation such as this, laminar flow of the electrolyte to the blind via is disrupted, further impacting uniform plating.

Other important considerations and conditions to be mastered include:

1. Ensure consistent lamination thicknesses for outer layers, otherwise laser drilling will be seriously affected.
2. Use caution on energy levels so that delamination or epoxy residue is not produced at the bottom of the blind vias.
3. Make careful selection of dielectrics to be laser drilled (laser-drillable prepreg).
4. Check the depth of field of the laser drill to verify the thickest board that can be laser drilled.
5. Fabricators must invest in latest registration and via formation equipment.

–         Hole and via positional accuracy is a possible issue

–         Systems available to predict material movement

Desmear and Metallization
From a pure materials standpoint, these higher performance resins are more difficult to desmear and metallize. Because the modulus is higher, the materials are more brittle. These materials are also more chemically resistant to chemical processes, including alkaline permanganate chemistries. One cannot rely on the high surface area and honey-combed texture on the resin that is common with lower Tg materials.

However, ensuring that drill smear and other debris are removed, the alkaline permanganate process must also activate both the resin and glass to enable the adhesion of subsequent copper plating. Loose debris and a smooth resin surface will not provide the necessary adhesion sufficient to withstand thermal excursions and mechanical shock.

In Part 2 of this series, I’ll be taking a deeper look at metallization.

References

1. Getting Started in HDI Fabrication, by Happy Holden and Michael Carano, internal publication, Feb 2021.

This column originally appeared in the February 2023 issue of PCB007 Magazine.