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Trouble in Your Tank: Implementing Direct Metallization in Advanced Substrate Packaging
iNEMI Packaging Tech Topic: Challenges and Solutions for AI Servers with Large Substrates
July 20, 2023 | iNEMIEstimated reading time: 1 minute
Increasingly, processors and memory are being packaged close together on a single substrate for applications such as AI servers. For example, on the Nvidia H100 the GPU is connected to six HBM3s on a CoWoS (chip-on-wafer-on-substrate). Processers with 12 or 16 HBMs (high bandwidth memories) will become common in the future, creating a demand for larger substrates, and as the substrate size becomes larger, there are challenges with fine lines, yield and flatness.
The conventional substrate is symmetrically built, with more than 10 layers of ABF on each side. However, most of the fine line interconnections need to be close to the chip side, and the ABF routing capability on the PCB side can only be used through the substrate core, which is not electrically desirable. A better way is to move more ABF layers from the bottom side of the core to the top side, but doing so creates a structure that is not symmetric and can result in substrate warpage.
SiPlus Co. has developed a structure and process for making an asymmetric thin film RDL (TFRDL) structure by connecting two RDL layers. In this configuration, the stress of each RDL layer can compensate for the other. On a 20x20mm test vehicle, SiPlus found that warpage was only +/-3um. The company has also developed a 2.0D integrated substrate structure where TFRDL is connected to ABF lamination layers without solders in between. A substrate size of 8 inches has been demonstrated with this technology.
Join us to learn more about SiPlus Co.’s integrated substrate technology.
About the Speaker
Dr. Dyi-Chung Hu, founder and CEO of of SiPlus Co., is an expert in substrate technology and the inventor of integrated substrate structures of 2.0D and 2.2D. SiPlus is devoted to developing innovative, high-performance, and light carbon footprint 2.XD solutions for semiconductor system integration.
Registration
This webinar is open to industry; advance registration is required (see link below). For additional information, please visit iNEMI's website.
Wednesday, July 19, 2023
9:00-10:00 a.m. EDT (US)
3:00-4:00 p.m. CEST (Europe)
10:00-11:00 p.m. JST (Japan)
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