-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueSignal Integrity
If you don’t have signal integrity problems now, you will eventually. This month, our expert contributors share a variety of SI techniques that can help designers avoid ground bounce, crosstalk, parasitic issues, and much more.
Proper Floor Planning
Floor planning decisions can make or break performance, manufacturability, and timelines. This month’s contributors weigh in with their best practices for proper floor planning and specific strategies to get it right.
Showing Some Constraint
A strong design constraint strategy carefully balances a wide range of electrical and manufacturing trade-offs. This month, we explore the key requirements, common challenges, and best practices behind building an effective constraint strategy.
- Articles
- Columns
- Links
- Media kit
||| MENU - design007 Magazine
Three Things to Improve High-Speed PCB Signoff, Part 2
September 27, 2023 | Brad Griffin, Cadence Design SystemsEstimated reading time: 1 minute

Another challenge for SerDes is losses within the channel design. At high speeds, dielectric material can be very lossy, making the appropriate selection of the right material, length, etc., critical for the channel. Many questions about stackup, trace widths, and height from the ground plane need to be defined up front. Simulating a signal with a topology explorer tool extracted from the design can be used to set up and run sweep parameters and push min/max length/spacing values into the Allegro schematic constraint manager (system capture). The preliminary constraints and schematics flow is illustrated in Figure 1. As the design progresses with final decisions on stackup and material selections, these constraints can be adjusted.
With the schematics phase finished and the layout phase in progress, the next challenge is compliance with specifications. Specs are dependent on the technology—PCI Express (PCIe), USB, etc.—and, because each one has its own requirements, this can be a complicated process. During this analysis, it is important to make sure the correct transmitter and receiver IBIS-AMI models are being used.
For the channel, Cadence tools can be used to accurately model the channels and address specifications. This is done by using the board file created by the layout designer, selecting several or all the lanes (depending on how much time is available), and running either a 2.5D or full 3D analysis on the entire channel.
Using the results of the channel extraction, a compliance analysis can be run based on the desired protocol. Most likely this will not be a one-time event, as often some obscure requirement not identified in the preliminary phase will surface, requiring additional iterations.
To read the rest of this article, which appeared in the September 2023 issue of Design007 Magazine, click here.
Testimonial
"The I-Connect007 team is outstanding—kind, responsive, and a true marketing partner. Their design team created fresh, eye-catching ads, and their editorial support polished our content to let our brand shine. Thank you all! "
Sweeney Ng - CEE PCBSuggested Items
Beyond Design: Slaying Signal Integrity Villains
09/17/2025 | Barry Olney -- Column: Beyond DesignHigh-speed PCB design is a balancing act, where subtle oversights can develop into major signal integrity nightmares. Some culprits lie dormant during early validation, only to reveal themselves later through workflow disruptions and elusive performance bottlenecks. Take crosstalk, for example. What begins as a stray signal coupling between traces can ripple through the design, ultimately destabilizing the power distribution network. Each of these troublemakers operates with signature tactics, but they also have well-known vulnerabilities.
Curing and Verification in PCB Shadow Areas
09/17/2025 | Doug Katze, DymaxDesign engineers know a simple truth that often complicates electronics manufacturing: Light doesn’t go around corners. In densely populated PCBs, adhesives and coatings often fail to fully cure in shadowed regions created by tall ICs, connectors, relays, and tight housings.
Knocking Down the Bone Pile: Best Practices for Electronic Component Salvaging
09/17/2025 | Nash Bell -- Column: Knocking Down the Bone PileElectronic component salvaging is the practice of recovering high-value devices from PCBs taken from obsolete or superseded electronic products. These components can be reused in new assemblies, reducing dependence on newly purchased parts that may be costly or subject to long lead times.
On the Line With… Podcast: UHDI and RF Performance
09/17/2025 | I-Connect007I-Connect007 is excited to announce the release of a new episode in its latest On the Line with... podcast series, which shines a spotlight on one of the most important emerging innovations in electronics manufacturing: Ultra-High-Density Interconnect (UHDI).
American Standard Circuits to Exhibit and Host Lunch & Learn at PCB West 2025
09/17/2025 | American Standard CircuitsAnaya Vardya, President, and CEO of American Standard Circuits/ASC Sunstone Circuits has announced that his company will once again be exhibiting at PCB West 2025 to be held at the Santa Clara Convention Center on Wednesday, October 1, 2025.