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At IPC APEX EXPO 2024 in Anaheim, California, five competitors squared off to determine who was the best of the best at PCB design.
As finalists in the third annual IPC Design Competition, the five designers were invited to IPC APEX EXPO to compete in a five-hour layout challenge, to place components and route a board, compliant to relevant IPC standards. As part of the finals heat, competitors used Altium Designer, and a project was provided with stackup and board geometry complete, with certain critical components pre-placed. All other components were left to be placed at the discretion of the competitors.
At the end of the round, each competitor delivered their project file to judges Kris Moyer and Patrick Crawford, IPC; Steve Roy, Roy Design and Manufacturing Service; Russell Steiner, Amphenol; Kevin Kusiak and David Caputa, Lockheed Martin. The judges placed weight on examining completeness of the board (i.e., how many routed nets) vs. critical errors – namely short circuits, clearance violations, via producibility, and various signal integrity aspects.
After an intense 2.5-hour judging process, Dinesh G., lead turnkey, Sienna ECAD, took first place with his PCB design.
Second place went to Paul Brionez, CID+, senior PCB design layout engineer, Wisk Aero. Third place went to Ajeesh Francis, senior PCB engineer, Tessolve Semiconductor Pvt. Ltd.
Runners-up included: Joseph Chiu, ToyBuilder Labs and Harish G., senior engineer, R&D-Mobility, Exicom Tele-Systems Ltd.
To learn more about IPC’s design initiative, visit ipc.org/solutions/ipc-design.
