Advanced Packaging for AI: Reliability Starts at the Cu/Cu/Cu Microvia Junction

Estimated reading time: 7 minutes

The rapid growth of AI computing, from training clusters to inference at scale, is reshaping demand across the entire electronics supply chain. Advances in technology requirements, such as higher bandwidth, lower latency, and greater compute density, are driving the development of advanced packaging technologies and transforming the PCB industry across design, manufacturing, testing, and even architecture.

As AI chips require enormous data movement and power delivery, 700 to 1,000 W per accelerator, the increased silicon content and the resulting push for higher IO density from chip to interposer, IC substrate, and PCB have a major impact on PCB architecture. This has led to the adoption of more complex hybrid constructions, including high-aspect-ratio multilayers and HDI build-ups. These changes result in more multilayer and HDI layer builds, higher-speed signal routing, the use of more advanced materials, and increased interconnect density on the PCB.

The PCB reliability is an integral part of system operation. However, the compounded effects of large temperature variations during operation and the mismatch in the coefficient of thermal expansion (CTE) as materials in PCBs expand at different rates (copper vs. epoxy resin in laminates) introduce additional stress. These factors significantly increase stress on the PCB and its interconnects, leading to interfacial delamination, crack propagation, and separation of blind microvias (BMVs). Stress concentrates at the BMV interfaces, leading to cracking and, eventually, open joints. As a result, BMV reliability has become a major concern for these complex hybrid PCBs. Therefore, understanding the various BMV interfaces, such as the copper capture pad, electroless copper, and electrolytic copper, is key to ensuring high-reliability PCBs.

Next, we will delve into the various aspects that influence BMV reliability.

Why the Recrystallization Path Decides Joint Life

After plating, copper moves from a fine‑grained, metastable state toward its final crystallized microstructure, and we typically see two outcomes in stacked BMVs:

• Epitaxial (“bottom‑up”) recrystallization: The electroless Cu layer crystal structure inherits the pad’s orientation, and the electrolytic Cu continues it. Interfaces fade, strain spreads, joints live longer.
• Non‑epitaxial (“top‑down”) recrystallization: Each layer crystallizes on its own. Boundaries stay distinct and potentially act as crack pathways.

Factors that influence a junction’s tendency to migrate toward one or the other are:

• The pad surface condition: Organic residues, oxides, or trapped process species can block the upward migration of the grain boundary diffusion front.
• Legacy chemistry: The additive/stabilizer balance in electroless and electrolytic Cu baths biases grain texture; some additive families promote or suppress epitaxy depending on grain and facet orientation of underlaying Cu-substrate.
• Thermal history: In HDI, the lamination press often supplies enough heat for recrystallization. Additional bake cycles mainly help outer layers. Maintaining cleanliness at the pad, employing wet-to-wet processes from electroless Cu to electrolytic Cu, and minimizing additive co-deposition can substantially enhance the likelihood of achieving a fully epitaxial junction and extend the lifespan under AI-class assembly profiles.

Early Screening With NCL

While full reliability tests such as hot-oil cycling, Highly Accelerated Stress Test (HAST), or reflow simulation per IPC-TM-650 remain the gold standard, these tests can be time-consuming and take many weeks. The Normalized Crack Length (NCL) method provides a practical, microstructure-based screening method for the early identification of interfaces. A higher NCL value obtained through this method is associated with a longer lifespan in thermal cycling datasets.  

The NCL method is a valuable tool for AI because it enables rapid discrimination between chemistries and processes that might otherwise appear similar, allowing for efficient identification of the most promising candidates prior to extensive qualification procedures. The NCL method does not replace physical testing; it triages which process leg deserves the next test, which is more expensive.

Nanovoids: Where They Appear Matters

High-resolution TEM/EDX analysis can reveal populations of nanovoids that may be overlooked by routine FIB/SEM methods. In this case, the location and impact on recrystallization can be equally as significant as the count alone. In a field study involving over 400 investigations, MKS' Atotech identified distinct nanovoid types at the Cu capture pad/electroless Cu/Cu via (Cu/Cu/Cu) junction and correlated each to root causes and their effect on recrystallization. The most significant class of brittle behavior is formed during electrolytic Cu initiation at the electroless Cu/electrolytic Cu interface. At this point, additive/halide transients can suppress epitaxy and create aligned, sized voids. Controlling the first micrometers of electro-deposition becomes essential, and therewith balancing additives and keeping a steady solution exchange.

Practical Controls for Optimal Outcomes

Based on field investigations and detailed studies, the following controls have been shown to reduce brittle interfacial failures and promote bottom-up recrystallization:

• Pad surface preparation: To ensure complete oxide removal with minimal air breaks, it is recommended to use a wet-in-wet transfer from electroless Cu to electrolytic Cu wherever possible. This will help to avoid reoxidation at a critical interface that must remain open for bottom-up recrystallization.  
• Electroless Cu chemistry and hydrodynamics: Cyanide-free systems have been shown to match the robustness of cyanide-stabilized baths. Both solution types benefit from effective liquid exchange into BMV bottoms to avoid near-pad depletion bands. It is essential to closely monitor co-deposited additives and/or H₂, as well as early porosity signatures, as these elements can serve as crucial indicators.
• Electrolytic Cu initiation discipline: The initial micrometers of electrolytic copper have a significant impact on whether epitaxy continues or stalls. Controlling the additive balance and current density ramp has been the most effective strategy against the interfacial voiding that leads to brittle failures.
• Thermal budget awareness: It is beneficial to utilize the lamination press heat to assist recrystallization where it already exists in the flow. Additionally, it is advisable to selectively evaluate additional bakes for outer layers rather than by default.
• Microstructure‑based screening: The use of the NCL method allows for the comparison of options that are similar in appearance. A D-SIMS scan through the junction should be done, as this clearly shows the origin of impurities and their precise location in the junction.

Implications for AI Packaging

The implications of this development for advanced packaging for AI are multifold:

• Reliability bottlenecks have shifted “down” into the board. The use of larger packages, finer pitches, and higher temperature assembly profiles has the potential to expose any weaknesses in the Cu/Cu/Cu junction. Consequently, the integrity of microvias at the board level has a direct impact on system reliability.
• Crystallization is a process that can be controlled. Maintaining clean interfaces and ensuring disciplined electroless Cu deposition and electrolytic Cu nucleation starts are practical, high-leverage steps that can lead to fully epitaxial structures.
• Take measurements at the outset and learn from them promptly. NCL provides a quantitative, faster way to rank similar microstructures before full reliability cycles are complete.

Summary

We've reached a point in AI hardware development where the bottleneck isn't always the chip itself; it's the board underneath it. Interconnect physics, specifically, how copper recrystallizes across the capture pad and at the interfaces between electroless Cu and electrolytic Cu in stacked BMVs, determines the reliability of the PCB and, in turn, the system. Failures, especially in AI server racks, are very costly given the investments involved.

After hundreds of investigations, a few things stand out. Epitaxy doesn't happen by accident; you must earn it: clean interfaces, no reoxidation, use of appropriate process chemistries, and disciplined control at the start of electroless Cu deposition and electrolytic Cu plating. Those first few micrometers matter more than most process engineers give them credit for.

Don't wait for full qualification cycles to tell you which tool and chemistry are working; the NCL method provides an understanding of the BMV Cu interface microstructure early enough to act on it. Leverage this approach and validate the PCB reliability with thermal cycling testing.

Finally, stop just counting nanovoids. While void density is an important factor, equally important is where the voids are in the Cu/Cu/Cu junction and what impact, if any, they have on overall recrystallization. The Cu/Cu/Cu junction is small, but in the AI rack, its reliability is critical to PCB reliability and uptime.

Resources

• “Nanovoid Formation at Cu/Cu/Cu Interconnections of Blind Microvias: A Field Study,” by T. Bernhard, IMAPS Proceedings, 2019.
• “A Review of Factors Effecting Crystallisation and Epitaxial Growth in Blind Micro Vias,” by R. Massey, IPC APEX EXPO Advanced Electronic Packaging Conference Technical Proceedings.
• “Copper Crystal Structures in Plated Microvias—Their Recrystallisation and a Means to Identify Joints at Risk of Premature Failure,” by T. Bernhard, ECTC related work.
• “Relation between surface morphology, facet selection, and crystal orientation in electroless copper deposits on polycrystalline copper substrates,” by R. Bruening, Thin Solid Films, 2026.

Kuldip Johal is CTO & VP, Business Development, at MKS’ Atotech.