Estimated reading time: 4 minutes

Hemant Shah on Cadence's FPGA-PCB Co-Design Suite

Cadence Design Solutions recently launched FPGA System Planner for the OrCAD and Allegro PCB platforms. Hemant Shah explains how this FPGA-PCB co-design suite can eliminate the need for designers to perform time-consuming manual pin assignments on high-pin-count FPGAs, as well as help detect errors early in the process.

Andy Shaughnessy: Today we're speaking with Hemant Shah, the product marketing manager for Allegro PCB products at Cadence Design Systems. How are you doing, Hemant?Hemant Shah: Great, Andy. Nice to talk to you again.Q. Hemant, Cadence had a pretty big announcement a few weeks ago, with the release of the FPGA System Planner, an FPGA-PCB co-design solution. Why don't you give us some background on this tool and explain what makes it important?

A. Sure. As you know, and as many of our customers know, FPGAs have been gaining in popularity for a long time. But, as FPGAs grow in their capacity and capability to do more complex applications, they tend to be larger in sizes with larger numbers of pin counts. And because of their increased capability, they provide more configurability for the end-user to use these FPGAs. When FPGAs get to the size of 500 pins, 750 pins or 1,000 pins, it's really difficult to do pin assignments manually. And pin assignments are needed because that's how you integrate any device, whether it be an FPGA or an ASICs device, onto the PCB design process. And so the FPGAs have been gaining in popularity, but the tools are not keeping up. There are many customers out there who use home-grown tools or even some of the competitors' tools. They're a good first step, but they're all manual, and when you deal with high-pin-count devices, complex devices, manual tools tend to be error-prone. And they can create problems for the design process. So a lot of our customers have been asking us to find a solution to bridge this design gap.Q. I understand Cadence worked with Taray Inc. and integrated Taray's technology into the System Planner.

A. We partnered with Taray because Taray had come up with this technology and worked with us and our customers. They worked with us and integrated it into our flow. So we OEMed their technology and integrated it even further than what we had done before. Taray was a partnership program member and we had done a lot of joint site visits and documented their technology and their approach.Q. So Hemant, how is this different from the other FPGA design tools on the market?

A. First, it allows FPGA designers to provide for relative placement of these FPGA devices so that when pin assignment is done, it's done with routing in mind. Second, it automates the pin assignment process using the connectivity that the user provides, the relative placement that's specified by the user. And the FPGA pin assignment rules are taken into account to automatically synthesize pin assignments for the FPGAs. So it's automation that's driven by placement, higher-level connectivity. It comes with a library of FPGA models that have FPGA vendor pin assignment rules encoded. This then drives the automation to get automatic pin assignments. And more importantly it's automated with routing in mind to make sure there's a minimum number of crossovers for the routing process. The FPGA designer is taking into account the PCB designers' challenges in routing large-pin-count devices. Those elements make it unique and different from anything else out there.

Q. Does the System Planner organize the schematic and PCB design data?

A. The way it works is: The FPGA designer can start doing this planning long before the schematic or PCB layout has been done. The FPGA designer can do the placement, do the pin assignment, and take the results of the automated pin assignment to the FPGA vendor tools to make sure there are no issues with internal timing of the FPGAs. Once the FPGA designer is satisfied with the pin assignment and the internal timing of the device, that pin assignment can be sent over to the schematic process by exporting synthesized schematics that have the FPGA symbols and the connectivity that's associated with it. The hardware designer can then take that FPGA subsystem, integrate it with the rest of the PCB system, and pass it on to the PCB layout system.Q. Does this makes it easier to catch errors in the process?A. Absolutely, this is one of the benefits. An FPGA can have multiple power voltages, multiple power supplies--for example DDR 2 or DDR3 may require different power voltages. If an incorrect power is associated with a power pin on an FPGA, often that's not caught through manual processes. With the FPGA pin assignment rules built into this system, and the higher-level connectivity that the user specifies, it allows FPGA System Planner to make sure that incorrect pin assignments don't happen.Q. What kind of customer was asking for this tool?A. Any customer that's using FPGAs was asking for this. Now, of course, if you're dealing with a very small, not very complex 100-pin FPGA, it's probably not as painful to design those in. But any time you go to about 300, 500 pins on an FPGA, and you have a lot of configurability, you want to be able to use this tool. There are two poor choices most people end up with: Either add the number of layers or increase the design cycle time. And we always felt going into this process that there was a better way to do this, and we worked with Taray to provide this solution to the market.Q. This is available on the Allegro and OrCAD platforms?A. Yes, and Allegro FPGA System Planner comes in three flavors: Allegro System Planner L, XL and GXL.Q. Thanks for speaking with us today, Hemant.A. Thank you, Andy.