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PDN Planning and Capacitor Selection, Part 1

In my first column on power distribution network (PDN) planning, Beyond Design: Power Distribution Network Planning, I described the basics of planning for low AC impedance between the planes, in order to reduce supply noise and provide reliable performance. I recommend that you read that column first to get the required background knowledge.

This column will focus on capacitor selection and three alternative approaches to analyzing the PDN:

1. Target frequency
2. One value capacitor per decade
3. Optimized value capacitor.

Traditionally, the target frequency approach has been used. This method targets a precise frequency and is used to reduce AC impedance and can also be used to reduce EMI within a specific band. The alternatives of using either one value capacitor per decade or many optimized capacitors, is an attempt to level out the AC impedance, at the desired impedance, over a broad frequency band.

The latest high-performance processors, with sub-nanosecond switching times, use low DC voltages with high transient currents and high clock frequencies to minimize the power consumption and hence, heat dissipated. Fast rise times, low output buffer impedance and the simultaneous switching of busses create high transient currents in the power and ground planes degrading performance and reliability of the product.

Poor PDN design can result in unusual, intermittent signal integrity issues including high crosstalk and excessive emission of radiation. It can be extremely difficult to track down the cause of such issues, so my recommendation is to plan the PDN design prior to place and route in a pre-layout analysis of the design.

Read the full column here.


Editor's Note: This column originally appeared in the December 2013 issue of The PCB Design Magazine.