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Designers Notebook: Defining Package Variations, Part 1
December 15, 2010 |Estimated reading time: 5 minutes
With a goal of reducing packaging costs and addressing the need for miniaturization, several semiconductor suppliers have adopted bottom surface termination configurations. These semiconductor package variations go by such diverse names as Quad Flat Pack No-Lead (QFN), Land Grid Array (LGA), Small Outline No-Lead (SON), Plastic Quad Flat No-Lead (PQFN), Micro Lead Frame Plastic (MLFP™), Micro Lead-Frame Package (MLP™) and many more.
Many of the QFN and SON devices utilize a copper lead-frame for die attach and wire-bond but, because the lead contacts do not protrude outside the body outline, they are classified as “leadless.” The terminations can be positioned on two sides, four sides or – with more complex high pin-count applications – multiple rows. Standards for these leadless package families extend a great deal of latitude for the suppliers. The JEDEC [1] organization’s JC-11 committee has developed guidelines that define several no-lead package outlines that allow variations for contact geometry, contact pitch and contact location in relation to the outer edge of the package unit (pullback or no-pullback). The no-pullback variation, for example, occurs when the bottom contact geometry is positioned evenly with the outer edge of the package outline. The pullback and no-pullback contact variations are compared in Figure 1. Figure 1: Comparing terminal-to-edge variations.
The definition JEDEC has developed for the SON package family is a “no-lead rectangular semiconductor package with metalized terminals on two sides of the bottom surface of the package.” JEDEC defines the QFN as a “no-lead semiconductor package with metalized terminals on four sides of the bottom surface of the package.” The terminal contacts located along the edges of the bottom surface of the QFN package body may be arranged in 1, 2 or 3 rows.
Typical of the single-row QFN, the multiple row QFN package is often a lead-frame-based product. The package assembly is typical of other lead-frame-based semiconductors. The die element is first bonded to the top surface of the die attach paddle (DAP) followed by wire-bond termination from the perimeter die-bond pads to the terminal contact features of the lead-frame. The package is completed when the plastic casing is molded around the die and wire-bond area, leaving only the bottom area of terminals and heat spreader exposed for solder attachment. When bottom surface of the DAP is exposed outside the mold compound, it serves as thermal transfer feature to conduct heat away from the die element and package body.
As noted, the lead-frame style QFN and SON are encapsulated in a transfer mold process. Two configurations are used in the mold process. One configuration is designed so that each package profile and outline is defined by the mold tool. The mold tool is designed to furnish a tapered side wall, leaving access to a slightly protruding (no-pullback) copper lead area. This variation can be singulated by punching or saw cutting. The no-pullback terminal allows the contact ends to be flush with the outside edge. The second mold variation furnishes a monolithic encapsulation over all device units requiring saw singulation compared in Figure 2. In the case of saw-singulated devices, the ends of the copper lead-frame structure will also remain exposed.
Figure 2: Comparing QFN/SON overmold variations.
The QFN and SON often qualify as a Chip Scale Package (CSP) because the outline of the package is often only slightly larger than the die element. The market growth for these products is due in part to their relatively small package outline; however, its low manufacturing cost is the key driver that has enabled widespread use of this package. Low package-level assembly cost may not automatically translate into overall low board-level manufacturing cost, since this package presents a number of challenges. In order to assist the PCB designer and assembly process engineer considering use of these package families, an IPC [2] task group was formed to develop a new document that furnishes both guidance and end-product requirements.
The result of this effort is the IPC-7093, a design and assembly process implementation document focusing exclusively on the no-lead package families. In developing the document it was decided to use a common name that would include a wide range of package types: Bottom Termination Component (BTC). This term generically includes all no-lead package types, since they require a common approach for design and assembly. Although many of the BTC devices utilize a copper lead-frame for die attach and wire-bond, other package variations adopt multilayer ceramic or organic substrate technology for packaging. The lead-frame type QFN package families are generally furnished with a contact pitch of 1.0 mm or less with a package outline ranging from (but not limited to) 3.0 mm square to 9.0 mm square.
The IPC-7093 document, although not a complete recipe for all no-lead component families, identifies many of the characteristics that influence the successful implementation of a robust and reliable assembly processes and provides guidance information to component suppliers regarding the issues being faced in the assembly process. Solder joint reliability remains a concern for the larger outline QFN package. The more traditional SMT leaded packages (SOIC, QFP) have relatively long and somewhat flexible leads.
The BTC packages, on the other hand, do not have a lead extension and form that can absorb stresses and strains introduced by differing coefficient of thermal expansion between the package and the substrate. This factor, combined with a very low stand-off height and the fact that a growing majority will be joined with a tin-rich RoHS-compliant solder alloy, leads one to expect a relatively shorter solder joint life, especially for products exposed to very harsh environments.
While the lack of traditional leads allows lower package thickness and better electrical and thermal performance, the low standoff height may also trap flux residue. And if the trapped flux is active, the corrosion potential is increased. Also, the potential for opens in solder joint is a key concern. It is paramount that the package and PCB be very flat to achieve a satisfactory mechanical and electrical interface.
In addition, to control the effects of the large surface area of the die attach pad during reflow soldering, it will be necessary to tailor the solder stencil pattern or alter the mating thermal plane on the PCB. Part II of this column will address land pattern and circuit routing recommendations for SON and QFN package types, while Part III will focus on the PCB designer’s role in accommodating the solder attachment process.
References:1. JEDEC is the acronym for Joint Electronic Device Engineering Council.2. IPC is the Association Connecting Electronics Industries.Vern Solberg is an independent technical consultant specializing in surface mount and microelectronic design and assembly process development. He may be contacted at (408) 568-3734 or vsolberg123@aol.com.